Mitsubishi 32172 User Manual

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Mitsubishi 32-bit RISC Single-chip Microcomputers

M32R Family M32R/ECU Series

32172

32173

Group

User's Manual

http://www.infomicom.maec.co.jp/indexe.htm

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the most current document available.

Rev. 1.0

Revision date: Oct. 5, 2001

Table of Contents

Summary of Contents for Mitsubishi 32172

Page 1 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/ECU Series 32172 32173 Group User’s Manual http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 1.0 Revision date: Oct. 5, 2001...
Page 2 The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or repro- • duce in whole or in part these materials.
Page 3 REVISION HISTORY 32172/32173 GROUP USER’S MANUAL Rev. Date Description Page Summary First edition issued 10/5/2001...
Page 4 How to read internal I/O register tables Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column...
Page 5: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW 1.1 Overview ........................ 1-2 1.1.1 M32R Family CPU Core ..............1-2 1.1.2 Built-in Multiply-Accumulate Operation Function ........ 1-3 1.1.3 Built-in Flash Memory and RAM ............1-3 1.1.4 Built-in Clock Multiplier Circuit ............1-4 1.1.5 Built-in Powerful Peripheral Functions ..........1-4 1.1.6 Built-in Full-CAN Function ..............
Page 6 2.6 Data Formats ......................2-7 2.6.1 Data Types ....................2-7 2.6.2 Data Formats .................... 2-8 CHAPTER 3 ADDRESS SPACE 3.1 Outline of the Address Space ................. 3-2 3.2 Operation Modes ....................3-5 3.3 Internal ROM and External Extended Areas ............3-8 3.3.1 Internal ROM Area ................
Page 7 4.9 Interrupt Handling ....................4-15 4.9.1 Reset Interrupt (RI) ................4-15 4.9.2 System Break Interrupt (SBI) .............. 4-16 4.9.3 External Interrupt (EI) ................4-18 4.10 Trap Handling ....................... 4-20 4.10.1 Trap (TRAP) ..................4-20 4.11 EIT Priority ......................4-22 4.12 Example of EIT Processing .................. 4-23 4.13 Precautions on EIT ....................
Page 8 6.4.1 Flash Mode Register ................6-4 6.4.2 Flash Status Registers ............... 6-5 6.4.3 Flash Control Registers ..............6-8 6.4.4 Virtual-flash L Bank Registers ............6-14 6.4.5 Virtual-flash S Bank Registers ............6-15 6.5 Programming the Internal Flash Memory .............. 6-16 6.5.1 Outline of Flash Memory Programming ..........
Page 9 8.3 Input/Output Port Related Registers ............... 8-6 8.3.1 Port Data Registers ................8-8 8.3.2 Port Direction Registers ..............8-9 8.3.3 Port Operation Mode Registers ............8-10 8.4 Port Peripheral Circuits ..................8-31 8.5 Precautions on Input/Output Ports ................. 8-39 CHAPTER 9 DMAC 9.1 Outline of DMAC ....................
Page 10 CHAPTER 10 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers ............... 10-2 10.2 Common Timer Unit ..................... 10-8 10.2.1 Register Map of the Common Timer Unit ......... 10-8 10.2.2 Prescaler Unit ................... 10-10 10.2.3 Input Processing Control Unit ............10-11 10.2.4 Output Flip-flop Control Unit .............
Page 11 10.6.1 Outline of the TOM ................10-75 10.6.2 Outline of Each TOM Operation Mode ..........10-77 10.6.3 TOM Related Register Map .............. 10-79 10.6.4 PWM Output Disable Registers ............10-82 10.6.5 PWM Output Disable Control Registers ........... 10-84 10.6.6 TOM Control Registers ..............10-88 10.6.7 TOM Counters ..................
Page 12 11.2.6 A-D Digital Input Control Registers ..........11-35 11.2.7 A-D Successive Approximation Registers ........11-36 11.2.8 A-D Comparate Data Registers ............11-38 11.2.9 10-bit A-D Data Registers ..............11-40 11.2.10 8-bit A-D Data Registers ..............11-42 11.3 Functional Description of the A-D Converters ............11-44 11.3.1 How to Find Analog Input Voltages ...........
Page 13 12.4.1 Initial Settings for CSIO Reception ........... 12-39 12.4.2 Starting CSIO Reception ..............12-41 12.4.3 Processing at End of CSIO Reception ..........12-41 12.4.4 About Successive Reception ............12-42 12.4.5 Flags Indicating the Status of CSIO Receive Operation ....12-43 12.4.6 Typical CSIO Receive Operation .............
Page 14 13.2.6 CAN Error Count Registers .............. 13-26 13.2.7 CAN Baud Rate Prescalers .............. 13-27 13.2.8 CAN Interrupt Related Registers ............13-28 13.2.9 CAN Mask Registers ................ 13-39 13.2.10 CAN Message Slot Control Registers ..........13-43 13.2.11 CAN Message Slots ............... 13-48 13.3 CAN Protocol .......................
Page 15 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) ......14-7 14.3.4 Operation of VER (Continuous Monitor) ........... 14-9 14.3.5 Operation of VEI (Interrupt Request) ..........14-10 14.3.6 Operation of RCV (Recover from Runaway) ........14-11 14.3.7 Method to Set a Specified Address when Using the RTD ....14-12 14.3.8 Resetting the RTD ................
Page 16 15.2.24 ABDLT Registers ................15-38 15.2.25 RSUMLT Registers ................ 15-39 15.2.26 SSLT Registers ................15-40 15.3 Initialization for PD Sensor Support ..............15-41 15.4 Precautions on Using the PD Module ..............15-44 CHAPTER 16 D-A CONVERTERS 16.1 Outline of the D-A Converters ................16-2 16.2 D-A Converter Related Registers ................
Page 17 CHAPTER 19 RAM BACKUP MODE 19.1 Outline ......................... 19-2 19.2 Example of RAM Backup when Power is Down ..........19-2 19.2.1 Normal Operating State ..............19-3 19.2.2 RAM Backup State ................19-4 19.3 Example of RAM Backup for Saving Power Consumption ........19-5 19.3.1 Normal Operating State ..............
Page 18 CHAPTER 22 POWER-UP/POWER-SHUTDOWN SEQUENCE 22.1 Configuration of the Power Supply Circuit ............22-2 22.2 Power-On Sequence ................... 22-3 22.2.1 Power-On Sequence When Not Using RAM Backup ....... 22-3 22.2.2 Power-On Sequence When Using RAM Backup ......22-4 22.3 Power-Shutdown Sequence ................22-5 22.3.1 Power-Shutdown Sequence When Not Using RAM Backup ....
Page 19 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing ..............Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/E Instruction Processing Time ............ Appendix 2-2 APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise ................ Appendix 3-2 Appendix 3.1.1 Reduction of Wiring Length ..........Appendix 3-2 Appendix 3.1.2 Inserting a Bypass Capacitor between VSS and VCC Lines ..
Page 20 *** This is a blank page *** (16)
Page 21: Overview
CHAPTER 1 CHAPTER 1 OVERVIEW 1.1 Overview 1.2 Block Diagram 1.3 Pin Functions 1.4 Pin Layout...
Page 22: M32R Family Cpu Core
1.1.1 M32R Family CPU Core (1) Uses the RISC architecture • The 32172/32173 are 32-bit, RISC single-chip microcomputers built around the M32R family CPU core (hereafter referred to as the "M32R") and incorporating flash memory, RAM, and various other peripheral functions... all integrated into a single chip.
Page 23: Built-In Multiply-Accumulate Operation Function
DSP. 1.1.3 Built-in Flash Memory and RAM • The 32172/32173 contains flash memory and RAM that can be accessed with no wait states, making it possible to build a high-speed embedded system. • The internal flash memory allows for on-board programming (you can write to it while being mounted on the printed circuit board).
Page 24: Built-In Clock Multiplier Circuit
1.1 Overview 1.1.4 Built-in Clock Multiplier Circuit • The 32172/32173 internally multiplies the frequency of the input clock signal by 4 (or by 2 for the internal peripheral clock). When the input clock frequency is 10.0 MHz, the CPU clock frequency is 40 MHz and that of the internal peripheral clock is 20 MHz.
Page 25: Built-In Full-Can Function
Overview 1.1 Overview completed or the transmit register becomes empty. (5) Built-in Real-time Debugger (RTD) • The Real-time Debugger (RTD) provides a function for accessing directly from the outside to the M32R/E's internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with external devices.
Page 26: Built-In Timer/Arithmetic Circuits For Pd (Phase Digital) Sensors
• When not using the PD circuit, the PD sensor-handling timers can be used as ordinary input measurement timers or input event counters. 1.1.9 Built-in Debug Function • The 32172/32173 supports the JTAG interface. Using this JTAG interface, the microcomputer can perform boundary scan test. Rev.1.0...
Page 27: Block Diagram
Overview 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32172/32173. The features of each block are outlined in Tables 1.2.1 to 1.2.3. 32172 32173 Internal Bus Interface M32R CPU Core (max 40MHz) DMAC Multiplier-...
Page 28 Overview 1.2 Block Diagram Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when CPU clock = 40 MHz) Logical address space: 4 Gbytes linear External extended area: Maximum 4 Mbytes External data bus: 16 bits •...
Page 29 • When not using the PD circuit, the above timers can be used as input measurement timers or input event counters • Two blocks of CAN modules, each with 16-channel message slots JTAG • Boundary scan function, Mitsubishi original SDI debug function included Rev.1.0...
Page 30: Pin Functions
Overview 1.3 Pin Functions 1.3 Pin Functions Figure 1.3.1 shows a pin function diagram of the 32172/32173. Table 1.3.1 provides a description of pin functions. P82 / TXD0 XOUT P83 / RXD0 Clock VCNT P84 / SCLKI 0 / SCLKO 0...
Page 31 Overview 1.3 Pin Functions P82 / TXD0 XOUT P83 / RXD0 Clock VCNT P84 / SCLKI 0 / SCLKO 0 Serial I/O Port 8 P85 / TXD1 OSC-VCC P86 / RXD1 OSC-VSS P87 / SCLKI 1 / SCLKO 1 Reset RESET P93 / RXD3 (/ AD0IN8) P94 / TXD6...
Page 32 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (1/6) Classification Pin Name Description Type Function Power supply VCCE Power supply –– Supplies power to external I/O ports (5 V). VCCI Power supply –– Supplies power to the internal logic (3.3 V). RAM power supply ––...
Page 33 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (2/6) Classification Pin Name Description Type Function Data bus DB0-DB15 Data bus Input/Output 16-bit data bus for connecting external devices. In write ___ ___ ___ ___ cycle, the CPU outputs BHW/BHE and BLW/BLE indicating the valid byte position to write on the 16-bit data bus.
Page 34 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (3/6) Classification Pin Name Description Type Function PD controller TIN0A, TIN0B Timer input Input PD0 sensor interface and timer input pin. TIN1A, TIN1B Timer input Input PD1 sensor interface and timer input pin. A-D converter AVCC0 Analog power ––...
Page 35 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (4/6) Classification Pin Name Description Type Function Serial I/O SCLKI4, Clock output Input For UART mode: Use inhibited (in input state) SCLKI5 For CSIO mode: Transmit/receive clock input when external clock is selected SCLKO4, Clock output Output...
Page 36 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (5/6) Classification Pin Name Description Type Function Real-time RTDTXD Transmit data Output Serial data output pin for the real-time debugger. debugger RTDRXD Received data Input Serial data input pin for the real-time debugger. RTDCLK Clock input Input...
Page 37 Overview 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (6/6) Classification Pin Name Description Type Function Input/output P41-P47 Input/output port 4 Input/Output Programmable input/output port. port P61-P64 Input/output port 6 Input/Output Programmable input/output port. (Note 1) (However, P64 is an input-only port.) P70-P77 Input/output port 7 Input/Output...
Page 38: Pin Layout
Overview 1.4 Pin Layout 1.4 Pin Layout Figure 1.4.1 shows a pin layout diagram of the 32172/32173. Table 1.4.1 lists a pin arrangement of the 32172/32173. JTMS JTCK P87/SCLKI1/SCLKO1 P86/RXD1 JTRST P85/TXD1 JTDO P84/SCLKI0/SCLKO0 JTDI P103/TO11 P83/RXD0 P104/TO12/SCLKI4 P82/TXD0 VCCE...
Page 39 Overview 1.4 Pin Layout Table 1.4.1 Pin Arrangement of the 144LQFP Package (1/2) Pin Name No. Pin Name No. Pin Name P221/CRX0 P05/DB5 VCCI P225/A12/CS2 P06/DB6 OSC-VSS P07/DB7 P174/TXD2 P10/DB8 P175/RXD2 XOUT P11/DB9 VCCE OSC-VCC P12/DB10 P82/TXD0 VCNT P13/DB11 P83/RXD0 P30/A15 P14/OB12 P84/SCLKI0/SCLKO0...
Page 40 Overview 1.4 Pin Layout Table 1.4.2 Pin Arrangement of the 144LQFP Package (2/2) Pin Name No. Pin Name No. Pin Name _____ RESET 111 JTRST 131 P137/TIN23 (/AD1IN14) MOD0 112 JTDO 132 VCCE MOD1 113 JTDI 133 P150/TIN8/TXD7 (/AD0IN15) 114 P103/TO11 134 P153/TIN9/RXD7 (/AD1IN15) ___ ___ VCCE...
Page 41 Overview 1.4 Pin Layout P117 P114 JTRST JTCK P102/TO0 /TO7 /TO4 P110/TO0 MOD1 TRDATA6 TRDATA5 /RXD3 P71/WAIT FVCC N.C. /RTDTXD /RXD5 /SCLKI5 (/AD0IN8) P115/TO5 P70/BCLK P73/HACK JTDO JTMS P100/TO8 P111/TO1 RESET /RXD6 /RTDCLK /TXD3 /SCLKO5 (/AD1IN8) P101/TO9 P116/TO6 N.C. N.C. N.C.
Page 42 Overview 1.4 Pin Layout Table 1.4.3 Pin Arrangement of the 175FBGA Package (1/2) Pin Name No. Pin Name No. Pin Name –– P36/A21 ______ P45/CS1 OSC-VSS TRCLK ______ N.C. P225/A12/CS2 P35/A20 N.C. N.C. P37/A22 ___ ___ VCCI P42/BHW/BHE –– P150/TIN8/TXD7(/AD0IN15) VCCE ––...
Page 43 Overview 1.4 Pin Layout Table 1.4.4 Pin Arrangement of the 175FBGA Package (2/2) Pin Name No. Pin Name No. Pin Name P26/A29 P05/DB5 P13/DB11 P27/A30 P06/DB6 P12/DB10 P00/DB0 P07/DB7 N.C. P25/A28 N.C. P17/DB15 –– AD0IN2 AD0IN0 –– AD0IN6 AD0IN4 –– AD1IN2 AD1IN0 ––...
Page 44 Overview 1.4 Pin Layout *** This is a blank page *** 1-24 Rev.1.0...
Page 45: Cpu Registers
CHAPTER 2 CHAPTER 2 2.1 CPU Registers 2.2 General-purpose Registers 2.3 Control Registers 2.4 Accumulator 2.5 Program Counter 2.6 Data Formats...
Page 46 2.1 CPU Registers 2.1 CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses.
Page 47: Control Registers
2.3 Control Registers 2.3 Control Registers There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. Control Registers Processor status Word Register Condition Bit Register...
Page 48: Processor Status Word Register: Psw (Cr0)
2.3 Control Registers 2.3.1 Processor Status Word Register: PSW (CR0) The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs.
Page 49: Condition Bit Register: Cbr (Cr1)
2.3 Control Registers 2.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC"...
Page 50: Accumulator
2.4 Accumulator 2.4 Accumulator The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0-7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed.
Page 51: Data Formats
2.6 Data Formats 2.6 Data Formats 2.6.1 Data Types There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements.
Page 52: Data Formats
2.6 Data Formats 2.6.2 Data Formats (1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register.
Page 53 2.6 Data Formats (2) Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00").
Page 54 2.6 Data Formats (3) Endian The following shows the generally used endian methods and the M32R family endian. Bit endian Byte endian (H'01) (H'01234567) B'0000001 Big endian H'01 H'23 H'45 H'67 Little endian B'0000001 H'45 H'23 H'01 H'67 Note: Even for bit big endian, H'01 is not B'10000000. Figure 2.6.4 Endian Methods M32R family 7700 family...
Page 55 2.6 Data Formats (4) Transfer instructions • Constant transfer LD24 Rdest, #imm24 imm24 LD24 Rdest, #imm24 Rdest, #imm16 Rdest Rdest, #imm8 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 Rdest • Register to register transfer Rdest, Rsrc Rdest, Rsrc Rsrc Rdest •...
Page 56 2.6 Data Formats (5) Memory (signed) to register transfer Memory Register • Signed 32 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc • Signed 16 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc Check the MSB 0 = positive 1 = negative •...
Page 57 2.6 Data Formats (7) Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Data in memory Data in register (R0-R15) Word data (32 bits) (R0-R15) Half-word data (16 bits) (R0-R15) Byte data (8 bits) MSB LSB...
Page 58 2.6 Data Formats This is a blank page. 2-14 Rev.1.0...
Page 59: Chapter 3 Address Space
CHAPTER 3 CHAPTER 3 ADDRESS SPACE 3.1 Outline of the Address Space 3.2 Operation Modes 3.3 Internal ROM and External Extended Areas 3.4 Internal RAM and SFR Areas 3.5 EIT Vector Entry 3.6 ICU Vector Table 3.7 Precautions on Address Space...
Page 60: Internal Rom Area
ADDRESS SPACE 3.1 Outline of the Address Space 3.1 Outline of the Address Space The logical addresses of the M32R are always handled in 32-bit width, providing a 4-Gbyte linear address space. The address space of the M32R consists of the following: (1) User space •...
Page 61 ADDRESS SPACE 3.1 Outline of the Address Space <Logical Space of the M32172F2> External Extended EIT Vector Entry Area (8 Mbytes) Logical Address H’0000 0000 H’0000 0000 User ROM Area (Note 1) H’0003 FFFF (16 Mbytes) H’0004 0000 Reserved Area (768 Kbytes) H’000F FFFF H’0010 0000...
Page 62 ADDRESS SPACE 3.1 Outline of the Address Space <Logical Space of the M32173F2> External Extended EIT Vector Entry Area (8 Mbytes) Logical Address H’0000 0000 H’0000 0000 User ROM Area (Note 1) H’0003 FFFF (16 Mbytes) H’0004 0000 Reserved Area (768 Kbytes) H’000F FFFF H’0010 0000...
Page 63 Section 6.5, "Programming the Internal Flash Memory." The locations of the internal ROM and external extended areas in the address space of the 32172/ 32173 vary depending on its operation mode. (All other areas in address space located the same way.) Also, during external extended mode, the available size of the external extended area varies...
Page 64 ADDRESS SPACE 3.2 Operation Modes Non-CS0 Area H'0000 0000 Internal ROM Area Internal ROM Area (256 Kbytes) (256 Kbytes) H'0003 FFFF H'0004 0000 Reserved Area (768 Kbytes) H'000F FFFF CS0 Area H'0010 0000 (2 Mbytes) CS0 Area (1 Mbytes) H'001F FFFF H'0020 0000 CS1 Area CS1 Area...
Page 65 ADDRESS SPACE 3.2 Operation Modes Pin functions (Note) A12 /CS2 A12/ CS2 A12/ CS2 A12 /CS2 A13 /CS3 A13 /CS3 A13/ CS3 A13/ CS3 H'0000 0000 Internal ROM Area Internal ROM Area Internal ROM Area Internal ROM Area H'0003 FFFF (256 Kbytes) (256 Kbytes) (256 Kbytes)
Page 66 The external extended area is available only when external extended or processor mode is selected for the chip operation mode. For access to the external extended area, the 32172/32173 outputs the control signals that are required for accessing an external device.
Page 67: Internal Ram And Sfr Areas
ADDRESS SPACE 3.4 Internal RAM and SFR Areas 3.4 Internal RAM and SFR Areas The 8-Mbyte area in user space addresses from H'0080 0000 to H'00FF FFFF is used for the internal RAM area and the SFR (Special Function Register) area. Of these, the space that the user can actually use is a 128-Kbyte area from H'0080 0000 to H'0081 FFFF, and the other addresses comprise ghost areas in units of 128 Kbytes.
Page 68 ADDRESS SPACE 3.4 Internal RAM and SFR Areas H'0080 0000 SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 Virtual-flash emulation area Internal RAM separated in units of 8 or 4 (32 Kbytes) Kbytes can be mapped into this area. For details, see Section 6.7. H'0080 BFFF Figure 3.4.2 Internal RAM Area and SFR (Special Function Register) Area of the M32173F2 3-10...
Page 69 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +0 address +1 address +0 address +1 address H’0080 0000 H’0080 0A00 Serial I/O4-7 Interrupt Controller H’0080 0A46 (ICU) H’0080 007E H’0080 0A80 H’0080 0080 A-D0 Converter A-D1 Converter H’0080 00EE H’0080 0AEE H’0080 0100 H’0080 0C8C Timers...
Page 70 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 Interrupt Mask Register (IMASK) H'0080 0004 H'0080 0006 SBI Control Register (SBICR) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) CAN0 Transmit/Receive &...
Page 71 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 8-bit A-D0 Data Register 1 (AD08DT1) H'0080 00D2 H'0080 00D4 8-bit A-D0 Data Register 2 (AD08DT2) H'0080 00D6 8-bit A-D0 Data Register 3 (AD08DT3) H'0080 00D8 8-bit A-D0 Data Register 4 (AD08DT4) H'0080 00DA 8-bit A-D0 Data Register 5 (AD08DT5)
Page 72 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 0400 DMA0-4 Interrupt Request Status Register (DM04ITST) DMA0-4 Interrupt Mask Register (DM04ITMK) H’0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) DMA0 Channel Control Register (DM0CNT) H’0080 0410 DMA0 Transfer Count Register (DM0TCT)
Page 73 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 DMA2 Transfer Count Register (DM2TCT) H’0080 0430 DMA2 Channel Control Register (DM2CNT) H’0080 0432 DMA2 Source Address Register (DM2SA) H’0080 0434 DMA2 Destination Address Register (DM2DA) H’0080 0436 DMA2 Request Cause Extension Register (DM2REQ) H’0080 0438...
Page 74 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 P22 Data Register (P22DATA) H’0080 0716 P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) H’0080 0720 H’0080 0722 P3 Direction Register (P3DIR) P2 Direction Register (P2DIR) H’0080 0724 P4 Direction Register (P4DIR) P7 Direction Register (P7DIR)
Page 75 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 0800 Input Processing Control Register 1 (TINCR1) Input Processing Control Register 0 (TINCR0) H’0080 0802 Input Processing Control Register 3 (TINCR3) Input Processing Control Register 2 (TINCR2) Input Processing Control Register 5 (TINCR5) H’0080 0804 Input Processing Control Register 4 (TINCR4)
Page 76 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 SIO67 Interrupt Status Register (SI67STAT) SIO47 Interrupt Mask Register (SI47MASK) H'0080 0A00 H'0080 0A02 SIO47 Receive Interrupt Cause Select Register (SI47SEL) H'0080 0A10 SIO4 Transmit Control Register (S4TCNT) SIO4 Transmit/Receive Mode Register (S4MOD) H'0080 0A12 SIO4 Transmit Buffer Register (S4TXB)
Page 77 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 8-bit A-D1 Data Register 0 (AD18DT0) H'0080 0AD0 H'0080 0AD2 8-bit A-D1 Data Register 1 (AD18DT1) 8-bit A-D1 Data Register 2 (AD18DT2) H'0080 0AD4 8-bit A-D1 Data Register 3 (AD18DT3) H'0080 0AD6 H'0080 0AD8 8-bit A-D1 Data Register 4 (AD18DT4)
Page 78 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 0C8C TID0 Counter (TID0CT) H’0080 0C8E TID0 Reload Register (TID0RL) TOM0_0 Reload Register (TOM00CT) H’0080 0C90 H’0080 0C92 H’0080 0C94 TOM0_0 Reload 1 Register (TOM00RL1) H’0080 0C96 TOM0_0 Reload 0 Register (TOM00RL0) H’0080 0C98...
Page 79 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address H'0080 0D8C TID1 Counter (TID1CT) H'0080 0D8E TID1 Reload Register (TID1RL) TOM1_0 Counter Register (TOM10CT) H'0080 0D90 H'0080 0D92 H'0080 0D94 TOM1_0 Reload 1 Register (TOM10RL1) H'0080 0D96 TOM1_0 Reload 0 Register (TOM10RL0) H'0080 0D98 TOM1_1 Counter (TOM11CT)
Page 80 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 1000 CAN0 Control Register (CAN0CNT) H’0080 1002 CAN0 Status Register (CAN0STAT) H’0080 1004 CAN0 Extended ID Register (CAN0EXTID) H’0080 1006 CAN0 Configuration Register (CAN0CONF) H’0080 1008 CAN0 Timestamp Count Register (CAN0TSTMP) H’0080 100A...
Page 81 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 CAN0 Message Slot 0 Standard ID1(C0MSL0SID1) CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) H'0080 1100 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) H'0080 1102 CAN0 Message Slot 0 Extended ID1(C0MSL0EID1) H'0080 1104 CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Extended ID2(C0MSL0EID2)
Page 82 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H'0080 1154 CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) H'0080 1156 CAN0 Message Slot 5 Data 1(C0MSL5DT1) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) H'0080 1158 CAN0 Message Slot 5 Data 3(C0MSL5DT3)
Page 83 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 CAN0 Message Slot 10 Data 3(C0MSL10DT3) CAN0 Message Slot 10 Data 2(C0MSL10DT2) H’0080 11A8 CAN0 Message Slot 10 Data 5(C0MSL10DT5) H’0080 11AA CAN0 Message Slot 10 Data 4(C0MSL10DT4) H’0080 11AC CAN0 Message Slot 10 Data 7(C0MSL10DT7) CAN0 Message Slot 10 Data 6(C0MSL10DT6)
Page 84 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 1400 CAN1 Control Register (CAN1CNT) H’0080 1402 CAN1 Status Register (CAN1STAT) H’0080 1404 CAN1 Extended ID Register (CAN1EXTID) H’0080 1406 CAN1 Configuration Register (CAN1CONF) H’0080 1408 CAN1 Timestamp Count Register (CAN1TSTMP) H’0080 140A...
Page 85 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 CAN1 Message Slot 0 Standard ID0(C1MSL0SID0) CAN1 Message Slot 0 Standard ID1(C1MSL0SID1) H'0080 1500 H'0080 1502 CAN1 Message Slot 0 Extended ID0(C1MSL0EID0) CAN1 Message Slot 0 Extended ID1(C1MSL0EID1) H'0080 1504 CAN1 Message Slot 0 Data Length Register (C1MSL0DLC) CAN1 Message Slot 0 Extended ID2(C1MSL0EID2)
Page 86 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 1554 CAN1 Message Slot 5 Data Length Register (C1MSL5DLC) CAN1 Message Slot 5 Extended ID2(C1MSL5EID2) H’0080 1556 CAN1 Message Slot 5 Data 1(C1MSL5DT1) CAN1 Message Slot 5 Data 0(C1MSL5DT0) H’0080 1558 CAN1 Message Slot 5 Data 3(C1MSL5DT3) CAN1 Message Slot 5 Data 2(C1MSL5DT2)
Page 87 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 CAN1 Message Slot 10 Data 3(C1MSL10DT3) CAN1 Message Slot 10 Data 2(C1MSL10DT2) H’0080 15A8 H’0080 15AA CAN1 Message Slot 10 Data 5(C1MSL10DT5) CAN1 Message Slot 10 Data 4(C1MSL10DT4) CAN1 Message Slot 10 Data 7(C1MSL10DT7) H’0080 15AC CAN1 Message Slot 10 Data 6(C1MSL10DT6)
Page 88 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 1800 Prescaler Register A (PRSA) Prescaler Register B (PRSB) H’0080 1802 DACNT Reload Register A (DACNTRL) TIN Input Processing Control Register (TINPDCR) H’0080 1804 TIN Interrupt Control Register (TINPDICR) TIN Interrupt Status Register (TINPDIST) H’0080 1806...
Page 89 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H’0080 1880 Prescaler Register 1C (PRS1C) SMSB Control Register 1 (SMSBCR1) H’0080 1882 TEP1M Control Register (TEP1MCR) TEP1P Control Register (TEP1PCR) H’0080 1884 TEP1P Counter (TEP1PCT) H’0080 1886 TEP1M Counter (TEP1MCT) H’0080 1888...
Page 90 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 D-A0 Conversion Register (DA0CNV) H’0080 1C78 H’0080 1C7A D-A1 Conversion Register (DA1CNV) H’0080 1C7C D-A Conversion Register (DACR) H’0080 1D00 D-A0 Data Register 0 (DA0DT0) D-A0 Data Register 1 (DA0DT1) H’0080 1D02 D-A0 Data Register 2 (DA0DT2)
Page 91 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 H'0080 1D50 D-A0 Data Register 80 (DA0DT80) D-A0 Data Register 81 (DA0DT81) H'0080 1D52 D-A0 Data Register 82 (DA0DT82) D-A0 Data Register 83 (DA0DT83) H'0080 1D54 D-A0 Data Register 84 (DA0DT84) D-A0 Data Register 85 (DA0DT85) H'0080 1D56...
Page 92 ADDRESS SPACE 3.4 Internal RAM and SFR Areas Address +0 address +1 address D7 D8 D-A0 Data Register 170 (DA0DT170) D-A0 Data Register 171 (DA0DT171) H'0080 1DAA H'0080 1DAC D-A0 Data Register 172 (DA0DT172) D-A0 Data Register 173 (DA0DT173) H'0080 1DAE D-A0 Data Register 174 (DA0DT174) D-A0 Data Register 175 (DA0DT175) H'0080 1DB0...
Page 93: Eit Vector Entry
ADDRESS SPACE 3.5 EIT Vector Entry 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/extended external areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here.
Page 94: Icu Vector Table
ADDRESS SPACE 3.6 ICU Vector Table 3.6 ICU Vector Table The ICU vector table is used by the internal Interrupt Controller. The start addresses of interrupt handlers for interrupt requests from internal peripheral I/Os are set at the corresponding addresses of this table, as shown below.
Page 95 ADDRESS SPACE 3.6 ICU Vector Table Address +0 address +1 address D7 D8 H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA A-D0 Conversion Interrupt Handler Start Address (A0-A15) H'0000 00CC A-D0 Conversion Interrupt Handler Start Address (A16-A31) H'0000 00CE H'0000 00D0 SIO0 Receive Interrupt Handler Start Address (A0-A15)
Page 96: Precautions On Address Space
3.7 Precautions on Address Space • Virtual-flash emulation function The 32172 has a function for mapping up to two 8-Kbyte blocks of the internal RAM beginning with the first address into the internal flash memory areas divided in units of 8 Kbytes (L banks).
Page 97: Chapter 4 Eit
CHAPTER 4 CHAPTER 4 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Accepting EIT Events Saving and Restoring PC and PSW EIT Vector Entry Exception Handling Interrupt Handling 4.10 Trap Handling 4.11 EIT Priority 4.12 Example of EIT Processing 4.13 Precautions on EIT...
Page 98 4.1 Outline of EIT 4.1 Outline of EIT If an event occurs while the CPU is executing an ordinary program, the CPU may have to suspend execution of the program and execute another program. Such an event is referred to by the generic name "EIT (Exception, Interrupt, Trap)."...
Page 99: Eit Events
4.2 EIT Events 4.2 EIT Events 4.2.1 Exceptions (1) Reserved Instruction Exception (RIE) A Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (an unimplemented instruction) is detected. (2) Address Exception (AE) An Address Exception (AE) occurs when access to an unaligned address is attempted in a Load or Store instruction.
Page 100: Eit Processing Procedure
4.3 EIT Processing Procedure 4.3 EIT Processing Procedure EIT processing consists of two parts, one automatically processed by hardware, and one processed by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. EIT request generated Program execution restarts...
Page 101 4.3 EIT Processing Procedure When an EIT is accepted, the M32R/E saves the PC and PSW to the stack (described later) and branches to the EIT vector. The EIT vector has entry addresses assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch addresses) for the EIT handler is written.
Page 102: Eit Processing Mechanism
4.4 EIT Processing Mechanism 4.4 EIT Processing Mechanism The EIT processing mechanism of the M32R/E consists of the M32R CPU Core unit and the internal peripheral I/O Interrupt Controller. It also has backup registers for the PC and PSW (BPC Register and the BPSW fild of the PSW register).
Page 103: Accepting Eit Events
4.5 Accepting EIT Events 4.5 Accepting EIT Events When an EIT event occurs, the M32R/E suspends execution of the program being executed and branches to EIT handler processing. The table below shows occurrence conditions of each EIT event and the timing at which they are accepted. Table 4.5.1 Accepting EIT Events EIT Event Processing Type...
Page 104: Saving And Restoring Pc And Psw
4.6 Saving and Restoring PC and PSW 4.6 Saving and Restoring PC and PSW The following describes the operations performed by the M32R when accepting an EIT and when executing the RTE instruction. (1) Hardware preprocessing when accepting an EIT (a) Save the PSW Register SM, IE, and C bits BSM ←...
Page 105 4.6 Saving and Restoring PC and PSW (a) Save the SM, IE, and C bits (c) Save the PC (d) Set the vector address in the PC (b) Update the SM, IE, and C bits Vector address Unchanged/0 (e) Restore the BSM, BIE, and BC bits (f) Restore the BPC value into the PC After executing the RTE instruction, the value of the BPC...
Page 106: Eit Vector Entry
4.7 EIT Vector Entry 4.7 EIT Vector Entry The EIT vector entry is placed in the user space beginning with address H'0000 0000. The EIT vector entry is listed below. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address Reset Interrupt H'0000 0000 Indeterminate (Note 1)
Page 107: Exception Handling
4.8 Exception Handling 4.8 Exception Handling 4.8.1 Reserved Instruction Exception (RIE) [Occurrence condition] A Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (an unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction.
Page 108 4.8 Exception Handling Address Address H'00 H'00 Return Return H'04 H'04 RIE occurred RIE occurred address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0020.
Page 109: Address Exception (Ae)
4.8 Exception Handling 4.8.2 Address Exception (AE) [Occurrence condition] An Address Exception (AE) occurs when access to an unaligned address is attempted in a Load or Store instruction. The following shows combinatorial instruction and address conditions under which an Address Exception is invoked. •...
Page 110 4.8 Exception Handling Address Address H'00 H'00 Return Return H'04 H'04 AE occurred AE occurred address address H'08 H'08 H'0C H'0C H'04 H'06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0030.
Page 111: Interrupt Handling
4.9 Interrupt Handling 4.9 Interrupt Handling 4.9.1 Reset Interrupt (RI) [Occurrence condition] _____ When input on RESET pin is pulled low, a Reset Interrupt (RI) is accepted unconditionally in each machine cycle. The Reset Interrupt has the highest priority of all EIT. [EIT processing] (1) Initializing the SM, IE, and C bits The PSW Register SM, IE, and C bits are initialized in the manner shown below.
Page 112: System Break Interrupt (Sbi)
4.9 Interrupt Handling 4.9.2 System Break Interrupt (SBI) The System Break Interrupt (SBI) is an emergency interrupt which is issued when power outage is detected or a fault condition is notified from an external watchdog timer. The System Break Interrupt cannot be masked with the PSW Register IE bit. Therefore, the System Break Interrupt can only be used when some fatal event has already occurred in the system when the interrupt is detected.
Page 113 4.9 Interrupt Handling [EIT processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← ← ← (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below.
Page 114: External Interrupt (Ei)
4.9 Interrupt Handling 4.9.3 External Interrupt (EI) An External Interrupt (EI) is generated based on interrupt requests output by the internal Interrupt Controller. The Interrupt Controller manages interrupt requests by means of 7-level interrupt priority. For details about the Interrupt Controller, refer to Chapter 5, "Interrupt Controller." For details about the causes of interrupts, refer to each relevant chapter where the internal peripheral I/ O in interest is described.
Page 115 4.9 Interrupt Handling [EIT Processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← ← ← (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below.
Page 116: Trap Handling
4.10 Trap Handling 4.10 Trap Handling 4.10.1 Trap (TRAP) [Occurrence condition] The Trap (TRAP) is a software interrupt, which is generated by executing the TRAP instruction. Sixteen types of Traps are generated corresponding to operands 0-15 of the TRAP instruction. Accordingly, there are sixteen vector entry addresses, one for each type of Trap.
Page 117 4.10 Trap Handling Address Address H'00 H'00 H'04 H'04 TRAP instruction TRAP instruction Return Return H'08 H'08 address address H'0C H'0C H'08 H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to user space addresses H'0000 0040 through H'0000 007C.
Page 118: Eit Priority
4.11 EIT Priority 4.11 EIT Priority The priority of EIT events is shown below. If two or more EIT events occur at the same time, the EIT with the highest priority of all is accepted first. Table 4.11.1 Priority of EIT Events and Manner of Return Priority EIT Event Processing Type...
Page 119: Example Of Eit Processing
4.12 Example of EIT Processing 4.12 Example of EIT Processing (1) When an RIE, AE, SBI, EI, or TRAP occurs singly IE=1 BPC Register = return address A IE=0 Occurrence of a single RIE, AE, SBI, EI, or If IE = 0 (remains unchanged), TRAP event nothing but reset and SBI are Return...
Page 120 4.12 Example of EIT Processing EIT vector entry BRA instruction (Other than SBI) (SBI) EIT handler Hardware Save BPC to stack (B)PSW preprocessing Save PSW to stack Processing of System Break Interrupt Save general-purpose Program being registers to stack executed •...
Page 121: Precautions On Eit
4.13 Precautions on EIT 4.13 Precautions on EIT The Address Exception (AE) requires caution because when an Address Exception occurs pursuant to execution of an instruction (one of the following three) that uses the "register indirect + register update" addressing mode, the value of the automatically updated register (Rsrc or Rsrc2) becomes indeterminate.
Page 122 4.13 Precautions on EIT *** This is a blank page *** 4-26 Rev.1.0...
Page 123 CHAPTER 5 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os 5.3 ICU Related Registers 5.4 ICU Vector Table 5.5 Description of Interrupt Operation 5.6 Description of System Break Interrupt (SBI) Operation...
Page 124: Outline Of The Interrupt Controller (Icu)
INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.1 Outline of the Interrupt Controller (ICU) The Interrupt Controller (ICU) controls maskable interrupts from internal peripheral I/Os and System Break Interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as External Interrupts (EI).
Page 125: Chapter 5 Interrupt Controller (Icu)
INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) Interrupt Controller System Break Interrupt request generated SBI Control Register SBIREQ (SBICR) To the CPU core Peripheral circuit Edge Interrupt request IREQ Maskable interrupt ILEVEL Edge Interrupt request requests generated IREQ Edge Interrupt request...
Page 126: Interrupt Sources Of Internal Peripheral I/Os
INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os 5.2 Interrupt Sources of Internal Peripheral I/Os The Interrupt Controller accepts as its input the interrupt requests from the timers, DMA, serial I/O, A-D converter, RTD, CAN, and PD controller. For details about these interrupts, refer to each relevant chapter where the internal peripheral I/O in interest is described.
Page 127 INTERRUPT CONTROLLER (ICU) 5.2 Interrupt Sources of Internal Peripheral I/Os Table 5.2.2 Interrupt Sources of Internal Peripheral I/Os (2/2) Interrupt Source Content No. of Type of Input Sources Input Source (Note) TOM0 output interrupt TOM0_0 to TOM0_7 output Level TOM1 output interrupt TOM1_0 to TOM1_7 output Level TMS0 output interrupt...
Page 128: Icu Related Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers 5.3 ICU Related Registers A register map associated with the Interrupt Controller (ICU) is shown below. +0 address +1 address Address H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 H'0080 0004 Interrupt Mask Register (IMASK) H'0080 0006 SBI Control Register (SBICR) CAN1 Transmit/Receive &...
Page 129: Interrupt Vector Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers 5.3.1 Interrupt Vector Register Interrupt Vector Register (IVECT) <Address: H'0080 0000> IVECT <When reset: Indeterminate> Bit Name Function 0-15 IVECT (ICU vector When an interrupt is accepted, – table address, this register stores the 16 low-order 16 low-order bits) bits of ICU vector table address for the accepted interrupt source.
Page 130: Interrupt Mask Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers 5.3.2 Interrupt Mask Register Interrupt Mask Register (IMASK) <Address: H'0080 0004> IMASK <When reset: H'07> Bit Name Function No functions assigned – IMASK (interrupt mask) 000: Disables maskable interrupt 001: Enables level 0 interrupt to be accepted 010: Enables level 0-1 interrupts to be accepted 011: Enables level 0-2 interrupts to be accepted 100: Enables level 0-3 interrupts to be accepted...
Page 131: Sbi (System Break Interrupt) Control Register
INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers 5.3.3 SBI (System Break Interrupt) Control Register SBI (System Break Interrupt) Control Register (SBICR) <Address: H'0080 0006> SBIREQ <When reset: H'00> Bit Name Function No functions assigned – SBIREQ (SBI request) 0: SBI not requested 1: SBI requested : Writable for only clearing (see the explanation below) The SBI (System Break Interrupt) is an interrupt generated by a falling edge of the SBI input signal.
Page 132: Interrupt Control Registers
INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers 5.3.4 Interrupt Control Registers CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR ) <Address: H'0080 0060> CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR ) <Address: H'0080 0061> PDC Compare Match & Error Interrupt Control Register (IPDCOPCR) <Address: H'0080 0062> RTD Interrupt Control Register (IRTDCR) <Address: H'0080 0063>...
Page 133 INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers D15) IREQ ILEVEL <When reset: H'07> Bit Name Function No functions assigned – (8-10) IREQ (interrupt request) 0 : Interrupt not requested (11) 1 : Interrupt requested No functions assigned – (12) ILEVEL 000: Interrupt priority level 0 (13-15) (interrupt priority level)
Page 134 INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers Interrupt request from each peripheral function IREQ Data bus D3,11 set/clear Interrupt enabled ILEVEL Interrupt priority D5-7,13-15 resolving circuit [0-7 levels] Figure 5.3.2 Configuration of the Interrupt Control Register (Edge Type) Interrupt request from each Group interrupt peripheral equipment group Read-only circuit...
Page 135 INTERRUPT CONTROLLER (ICU) 5.3 ICU Related Registers (2) ILEVEL (interrupt priority level) (D5-D7 or D13-D15) These bits set the priority level of an interrupt request from each internal peripheral I/O. Set the priority level to 7 to disable the interrupt from internal peripheral I/O or 0-6 to use the interrupt. When an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK value to determine whether to forward an EI request to the CPU or keep it pending.
Page 136: Icu Vector Table
INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table 5.4 ICU Vector Table The ICU vector table is used to set the start address of the interrupt handler for each internal peripheral I/O. The 31 interrupt sources are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Interrupt Source ICU Vector Table Address...
Page 137 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 address +1 address H'0000 0094 PDC Input & Error Detection Interrupt Handler Start Address (A0-A15) H'0000 0096 PDC Input & Error Detection Interrupt Handler Start Address(A16-A31) PWM Off Input Interrupt Handler Start Address (A0-A15) H'0000 0098 PWM Off Input Interrupt Handler Start Address (A16-A31) H'0000 009A...
Page 138 INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table Address +0 address +1 address H'0000 00C8 DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CA A-D0 Conversion Interrupt Handler Start Address (A0-A15) H'0000 00CC A-D0 Conversion Interrupt Handler Start Address (A16-A31) H'0000 00CE H'0000 00D0 SIO0 Receive Interrupt Handler Start Address (A0-A15)
Page 139: Description Of Interrupt Operation
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5 Description of Interrupt Operation 5.5.1 Accepting Interrupts from Internal Peripheral I/O An interrupt from any internal peripheral I/O is accepted when its priority level is found to be higher than the IMASK value by comparing its ILEVEL set value in the Interrupt Control Register and the Interrupt Mask Register's IMASK value.
Page 140 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.1 Fixed Hardware Priority Priority Interrupt Source ICU Vector Table Address Type of Input Source High PDC input & error detection interrupt H'0000 0094 – H'0000 0097 Level PWM off input interrupt H'0000 0098 –...
Page 141 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.2 ILEVEL Settings and the Accepted IMASK Values ILEVEL set value IMASK values at which interrupts are accepted (ILEVEL = "000") Accepted when IMASK is 1-7 (ILEVEL = "001") Accepted when IMASK is 2-7 (ILEVEL = "010") Accepted when IMASK is 3-7 (ILEVEL = "011")
Page 142: Processing Of Internal Peripheral I/O Interrupts By Handler
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing of Internal Peripheral I/O Interrupts by Handler (1) Branching to the interrupt handler When the CPU accepts an interrupt, it branches to the EIT vector entry after performing hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry assigned to the External Interrupt (EI) resides at address H'0000 0080, at which the instruction for branching to the beginning of the interrupt handler routine for the External Interrupt is written by the user.
Page 143 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation EI (External Interrupt) vector entry H'0000 0080 BRA instruction EI (External Interrupt) handler Save BPC to stack Save PSW to stack (Note) Program Save general-purpose being registers to stack executed Read Interrupt Mask H'0080 0004 IMASK Register (IMASK) and...
Page 144: Description Of System Break Interrupt (Sbi) Operation
INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation 5.6.1 Accepting SBI Interrupt The System Break Interrupt (SBI) is an emergency interrupt issued when power outage is detected or a fault condition is notified from an external watchdog timer. The SBI interrupt is always accepted by a falling edge of the SBI signal regardless of how the PSW Register IE bit is set, and cannot be masked.
Page 145: Chapter 6 Internal Memory
CHAPTER 6 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.2 Internal RAM 6.3 Internal Flash Memory 6.4 Internal Flash Memory Related Registers 6.5 Programming the Internal Flash Memory 6.6 Boot ROM 6.7 Virtual-flash Emulation Function 6.8 Connecting a Serial Programmer 6.9 Precautions on Rewriting Flash Memory...
Page 146 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.1 Outline of the Internal Memory The M32172F2/M32173F2 contains the following types of memory: • 16-Kbyte RAM for the M32172F2 or 32-Kbyte RAM for the M32173F2 • 256-Kbyte flash memory 6.2 Internal RAM Specifications of the internal RAM are shown below.
Page 147 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers 6.4 Internal Flash Memory Related Registers A register map associated with the internal flash memory is shown below. Address +0 address +1 address Flash Mode Register Flash Status Register 1 H'0080 07E0 (FMOD) (FSTAT1) Flash Control Register 1...
Page 148: Flash Mode Register
INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers 6.4.1 Flash Mode Register Flash Mode Register (FMOD) <Address: H'0080 07E0> FPMOD <When reset: H'0?> Bit Name Function No functions assigned – FPMOD 0: FP pin = low – (External FP pin status) 1: FP pin = high The Flash Mode Register (FMOD) is a read-only status register, with FPMOD showing the status of the FP (Flash Protect) pin.
Page 149: Flash Status Registers
6.4 Internal Flash Memory Related Registers 6.4.2 Flash Status Registers The 32172/32173 has two registers to show the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself.
Page 150 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers Flash Status Register 2 (FSTAT2) FBUSY ERASE WRERR1 WRERR2 <When reset: H'80> Bit Name Function FBUSY 0: Being programmed or erased – (Flash busy) 1: Ready state No functions assigned – ERASE 0: Erase normally operating or finished –...
Page 151 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers (4) WRERR2 (program operating status 2) bit (D12) The WRERR2 bit is used to determine whether an error occurred after the CPU has finished programming the flash memory. The programming operation terminated normally when WRERR2 = 0 or terminated in an error when WRERR2 = 1.
Page 152: Flash Control Registers
INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers 6.4.3 Flash Control Registers Flash Control Register 1 (FCNT1) <Address:H'0080 07E2> FENTRY FEMMOD <When reset: H'00> Bit Name Function No functions assigned – FENTRY 0: Normal read (Flash mode entry) 1: Erase/program possible No functions assigned –...
Page 153 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is at the flash memory address H'0000 0080. To run the flash rewrite program in RAM while the FENTRY bit = 1, the EI vector entry is at the RAM address H'0080 4000, in which case flash rewrite operation can be controlled using an interrupt.
Page 154 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers Flash Control Register 2 (FCNT2) <Address: H'0080 07E3> FPROT <When reset: H'00> Bit Name Function 8-14 No functions assigned – FPROT 0: Enables protection by lock bits (Unlock) 1: Disables protection by lock bits The Flash Control Register 2 (FCNT2) controls flash memory protection by lock bits (disables the internal flash memory against erase/programming).
Page 155 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers Flash Control Register 3 (FCNT3) <Address: H'0080 07E4> FELEVEL <When reset: H'00> Bit Name Function No functions assigned – FELEVEL 0: Normal level (Erase margin up) 1: Increases erase margin The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with an erase command.
Page 156 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers Flash Control Register 4 (FCNT4) <Address: H'0080 07E5> FRESET <When reset: H'00> Bit Name Function 8-14 No functions assigned – FRESET 0: No operation (Reset flash) 1: Resets the flash memory The Flash Control Register 4 (FCNT4) controls canceling the erase or program operation in the middle or initializing each status bit of Flash Status Register 2 (FSTAT2).
Page 157 INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers FENTRY=0 FENTRY=1 Program/erase flash memory Error detected Program/erase operation terminated normally FRESET=1 FRESET=0 Program/erase flash memory Figure 6.4.3 Example for Using the FCNT4 Register 6-13 Rev.1.0...
Page 158: Virtual-Flash L Bank Registers
INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers 6.4.4 Virtual-flash L Bank Registers Virtual-flash L Bank Register 0 (FELBANK0) <Address: H'0080 07E8> Virtual-flash L Bank Register 1 (FELBANK1) <Address: H'0080 07EA> Virtual-flash L Bank Register 2 (FELBANK2) <Address: H'0080 07EC> LBANKAD <When reset: H'0000>...
Page 159: Virtual-Flash S Bank Registers
INTERNAL MEMORY 6.4 Internal Flash Memory Related Registers 6.4.5 Virtual-flash S Bank Registers Virtual-flash S Bank Register 0 (FESBANK0) <Address: H'0080 07F0> Virtual-flash S Bank Register 1 (FESBANK1) <Address: H'0080 07F2> SBANKAD <When reset: H'0000> Bit Name Function MODENS 0: Disables virtual-flash function (Virtual-flash emulation enable) 1: Enables virtual-flash function No functions assigned...
Page 160: Programming The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5 Programming the Internal Flash Memory 6.5.1 Outline of Flash Memory Programming There are following two methods for writing to the internal flash memory. (1) When no write programs exist in the internal flash memory Set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot mode.
Page 161 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Flash E/W enable mode Normal mode (FENTRY=1) (FENTRY=0) H'0000 0000 H'0000 0000 EI vector entry ( H'0000 0080 ) Internal ROM area Internal ROM area EI vector entry H'0080 3FFF H'0080 3FFF ( H'0080 4000 ) H'0080 4000 H'0080 4000...
Page 162 (1) When the write programs do not exist in the internal flash memory Use the program in the boot ROM located on the 32172/32173 memory map to write to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode.
Page 163 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Negate reset Negate reset (start the boot program) POWER ON Select mode Select mode RESET MOD0 MOD1 Set up using the boot program FENTRY Write to the flash memory using the boot program Figure 6.5.3 Timing at Which Writing to the Internal Flash Memory (when no write programs exist in the flash memory) 6-19...
Page 164 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) When a write program already exists in the internal flash memory Use the write program available in the internal flash memory to write to the flash memory. For this write operation, use the internal peripheral circuits as needed for the system to which you are writing.
Page 165 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Flash mode Flash mode Flash rewrite starts RESET "H"or"L" "L" MOD0 MOD1 "H"or"L" (Single-chip or external extended mode) "H"or"L" Set up using the flash write program FENTRY Write to the flash memory using the flash write program Transfer the flash rewrite program to the RAM Figure 6.5.5 Timing at Which Writing to the Internal Flash Memory...
Page 166: Controlling Operation Modes During Flash Programming
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.2 Controlling Operation Modes during Flash Programming Chip operation modes are set using MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. Operation modes during flash programming are listed below. Table 6.5.1 Setting Operation Modes during Flash Programming MOD0 MOD1 FENTRY (Note)
Page 167 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) Entering flash E/W enable mode The microcomputer can enter flash E/W enable mode only when it is operating in single-chip or external extended mode. The microcomputer enters flash E/W enable mode only when the FP pin is at the high level and the Flash Control Register 1 (FCNT1) FENTRY bit = 1, and cannot enter flash E/W enable mode when operating in processor mode or the FP pin is low.
Page 168 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Go to one of the following modes • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode • External extended mode + flash E/W enable mode FMOD(H’0080 07E0) FPMOD...
Page 169: Procedure For Programming The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.3 Procedure for Programming the Internal Flash Memory To program the internal flash memory, use the flash write program which has been transferred from the flash memory into the internal RAM after entering flash E/W enable mode. In flash E/W enable mode, unlike in normal mode, data cannot be read from the internal flash memory and, hence, no programs in the flash memory can be executed.
Page 170 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) Page Program command The flash memory is programmed in units of pages, each page consisting of 256 bytes (lower address H'00-H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then write the program data to the desired flash memory address.
Page 171 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Internal flash memory area (256 KB) H’0000 0000 16KB Block 0 H’0000 3FFF H’0000 4000 Block 1 H’0000 5FFF Uneven blocks H’0000 6000 Block 2 H’0000 7FFF H’0000 8000 32KB Block 3 H’0000 FFFF H’0001 0000 64KB...
Page 172 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (4) Block Erase command The Block Erase command erases the contents of the internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the confirm command data H'D0D0 to the last even address of the memory block to be erased.
Page 173 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (8) Read Lock Bit Status command The Read Lock Bit Status command is used to verify whether memory blocks are protected (against write/erase) or not protected. Write the command data H'7171 to any address of the internal flash memory.
Page 174 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Follow the procedure below to write to the lock bits. a) Setting the lock bits to 0 (protect a memory block) Issue the lock bit program command (H'7777) to the memory block to be protected. b) Setting the lock bits to 1 (unprotect a memory block) Set the Flash Control Register 2 FPROT bit to 1 to disable protection by lock bits, then use the Block Erase command (H'2020) or Erase All Unlock Blocks command (H'A7A7)
Page 175 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write Page Program command (H’4141) to any internal flash memory address Write data to the desired internal flash memory address (Note 1) Increment the previous write address by 2 and write the next data to the new address Finished writing for one page? Data is written to the internal flash...
Page 176 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write Lock Bit Program command (H’7777) to any internal flash memory address Write Verify command (H’D0D0) to the last even address of the memory block to be protected Data is written to the lock bits by program (Note 1) Wait for 1 µs (as counted by hardware or...
Page 177 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write Block Erase command (H’2020) to any internal flash memory address Write Verify command (H’D0D0) to the last even address of the memory block to be erased Flash memory contents are erased by erase program (Note 1) Wait for 1 µs (as counted by hardware or...
Page 178 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write Erase All Unlock Blocks command (H’A7A7) to any internal flash memory address Write Verify command (H’D0D0) to any address of the memory blocks to be erased Flash memory contents are erased by erase program (Note 1) Wait for 1 µs (as counted by hardware or...
Page 179 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write Read Status Register command (H'7070) to any internal flash memory address Read any internal flash memory address Figure 6.5.13 Read Status Register Command START Write Clear Status Register command (H'5050) to any internal flash memory address Figure 6.5.14 Clear Status Register Command START Write Read Lock Bit Status Register...
Page 180: Flash Programming Time (Reference Data)
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.4 Flash Programming Time (Reference Data) The time required for programming the internal flash memory is described below for your reference. (1)M32172F2 and M32173F2 SIO transfer time (when transfer data size = 256 KB) 1/57600bpsx 1 (frame) x 11 (number of transfer bits) x 256 KB 50.1 [s] Flash programming time...
Page 181: Boot Rom
INTERNAL MEMORY 6.6 Boot ROM 6.6 Boot ROM Specifications of the boot ROM are shown below. Table 6.6.1 Specifications of the boot ROM Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait cycles (when internal CPU memory clock = 40 MHz) Internal bus connection Connects to a 32-bit bus...
Page 182: Virtual-Flash Emulation Function
INTERNAL MEMORY 6.6 Boot ROM 6.7 Virtual-flash Emulation Function The microcomputer can map 8-Kbyte blocks of internal RAM (up to two for the M32172F2 or up to three for the M32173F2) beginning with the start address into the internal flash memory area divided in units of 8-kbytes (L banks), and can map 4-Kbyte blocks of internal RAM (up to two for the M32173F2) beginning with address H'0080 A000 into the internal flash memory area divided in units of 4-kbyts (S banks).
Page 183 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function H’0080 4000 RAM bank L block 0 (FELBANK0) 8 Kbytes H’0080 6000 RAM bank L block 1 (FELBANK1) 8 Kbytes H’0080 8000 RAM bank L block 2 (FELBANK2) 8 Kbytes H’0080 A000 RAM bank S block 0 (FESBANK0) 4 Kbytes H’0080 B000...
Page 184: Virtual-Flash Emulation Areas
INTERNAL MEMORY 6.7 Virtual-flash Emulation Function 6.7.1 Virtual-Flash Emulation Areas The following shows the areas effective for the virtual-flash emulation function. Using the Virtual-Flash L Bank Registers, select 8-Kbyte blocks L banks of flash memory, one for each register (by setting the seven bits A12-A18 of start address of the desired L bank in the Virtual- Flash L Bank Register LBANKAD bits).
Page 185 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function <Internal flash> H'0000 0000 L bank 0 (8 Kbytes) L bank 1 H'0000 2000 (8 Kbytes) H'0000 4000 L bank 2 <Internal RAM> (8 Kbytes) 8 Kbytes H'0080 4000 H'0080 6000 8 Kbytes H'0003 C000 L bank 30 (8 Kbytes) H'0003 E000...
Page 186 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function <Internal flash> H’0000 0000 S bank 0 (4 Kbytes) H’0000 1000 S bank 1 (4 Kbytes) H’0000 2000 S bank 2 <Internal RAM> (4 Kbytes) H’0080 4000 8 Kbytes 8 Kbytes 8 Kbytes H’0080 A000 4 Kbytes H’0003 E000 S bank 62...
Page 187 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function Start address of flash Values set with L bank L bank memory bank address (LBANKAD) bits L bank 0 H’0000 0000 H’00 (Note) L bank 1 H’0000 2000 H’02 L bank 2 H’0000 4000 H’04 L bank 30 H’0003 C000...
Page 188 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function Start address of flash Values set with L bank S bank memory bank address (SBAKNKAD) bits S bank 0 H’0000 0000 H’00 (Note) S bank 1 H’0000 1000 H’01 S bank 2 H’0000 2000 H’02 S bank 62 H’0003 E000...
Page 189: Transition To Virtual-Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual-flash Emulation Function 6.7.2 Transition to Virtual-Flash Emulation Mode To enter virtual-flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering virtual-flash emulation mode, set the Virtual-Flash Bank Register MODEN bit to 1 to enable the virtual-flash emulation function.
Page 190: Application Example For Virtual-Flash Emulation Mode
INTERNAL MEMORY 6.7 Virtual-flash Emulation Function 6.7.3 Application Example for Virtual-Flash Emulation Mode By locating two RAM areas in the same virtual-flash area using the Virtual-Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx Initial value...
Page 191 INTERNAL MEMORY 6.7 Virtual-flash Emulation Function (4) Program operation with RAM block 1 Flash Replace Bank xx Initial value RAM block 1 Specify bank xx RAM block 0 Data write to RAM0 RAM block 1 (5) Changing program operation from RAM block 1 to RAM block 0 Flash Replace Bank xx...
Page 192: Connecting A Serial Programmer
INTERNAL MEMORY 6.8 Connecting a Serial Programmer 6.8 Connecting a Serial Programmer To rewrite the internal flash memory using a general-purpose serial programmer in boot mode + flash E/W enable mode, pins on the microcomputer listed below need to be processed to be suitable for use with the serial programmer.
Page 193 Note 5: The typical pullup resistance values for P84, P86, and P87 are 4.7 to 10 kΩ. Note 6: The status of the ports not shown above do not affect writing to the flash memory. Figure 6.8.1 Pin Connection Diagram for the 32172 6-49...
Page 194: Precautions On Rewriting Flash Memory
INTERNAL MEMORY 6.9 Precautions on Rewriting Flash Memory 6.9 Precautions on Rewriting Flash Memory The following describes precautions to be observed when rewriting the internal flash memory using a serial programmer in boot mode + flash E/W enable mode. • When you use the pins with the system that are used by a serial programmer, take measures not to affect the system when connecting a serial programmer.
Page 195: Outline Of Reset
CHAPTER 7 CHAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State Immediately after Reset 7.4 Precautions to Be Taken Immediately after Reset...
Page 196: Power-On Reset
RESET 7.1 Outline of Reset 7.1 Outline of Reset _____ The microcomputer is reset by applying a low-level signal to the RESET input pin. The _____ microcomputer is gotten out of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry.
Page 197: Internal State Immediately After Reset
RESET 7.3 Internal State Immediately after Reset 7.3 Internal State Immediately after Reset The table below shows the internal state of the microcomputer immediately after reset. For details about the initial state of internal peripheral I/O registers, refer to the relevant section of this manual where each internal peripheral I/O in interest is described.
Page 198 RESET 7.3 Internal State Immediately after Reset Table 7.3.2 Pin Status When Reset Pin name Single chip mode External extended mode Microprocessor mode Boot RESET, MOD0, Input Input Input Input MOD1, and FP Port P0, P1 Input Input Input Input P2, P3 Input Input...
Page 199: Precautions To Be Taken Immediately After Reset
RESET 7.4 Precautions to Be Taken Immediately after Reset 7.4 Precautions to Be Taken Immediately after Reset • Input/output ports After reset release, its input/output ports are disabled against input in order to prevent electric current from flowing through the pins. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN)'s PIEN0 bit.
Page 200 RESET 7.4 Precautions to Be Taken Immediately after Reset *** This is a blank page *** Rev.1.0...
Page 201: Outline Of Input/Output Ports
CHAPTER 8 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits 8.5 Precautions on Using Input/ Output Port...
Page 202 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32172/32173 has a total of 99 input/output ports connecting to external pins, comprised of P0- P13, P15, P17, and P22 (with P5 reserved for future use). These input/output ports can be used as input ports or output ports by setting up the direction registers.
Page 203 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of the Input/Output Ports Item Specification Number of ports Total 99 bits (Note 1) P00-P07 (8 bits) P10-P17 (8 bits) P20-P27 (8 bits) P30-P37 (8 bits) P41-P47 (7 bits) P61-P64 (4 bits)
Page 204 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal lines (or triple functions sharing the pin with two or more functions of peripheral I/O).
Page 205 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Chip operation DB10 DB11 DB12 DB13 DB14 DB15 mode settings (Note1) Input/output port operation mode register settings (Note2) BLW / BHW / A13 / (Reserved) (P61) (P62) (P63) BCLK / HACK / WAIT HREQ RTDTXD...
Page 206 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The input/output port related registers consist of the Port Data Register, Port Direction Register, and Port Operation Mode Register. Ports P0-P4 and P225 have their pin functions determined depending on CPU operation mode (selected with the FP, MOD0, and MOD1 pins).
Page 207 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Address +0 Address +1 Address H’0080 0740 P0 Operation Mode Register (P0MOD) P1 Operation Mode Register (P1MOD) H’0080 0742 P2 Operation Mode Register (P2MOD) P3 Operation Mode Register (P3MOD) H’0080 0744 Port Input Function Enable Register (PIEN) P4 Operation Mode Register (P4MOD) H’0080 0746...
Page 208: Port Data Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.1 Port Data Registers P0 Data Register (P0DATA) <Address : H'0080 0700> P1 Data Register (P1DATA) <Address : H'0080 0701> P2 Data Register (P2DATA) <Address : H'0080 0702> P3 Data Register (P3DATA) <Address : H'0080 0703>...
Page 209: Port Direction Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) <Address : H'0080 0720> P1 Direction Register (P1DIR) <Address : H'0080 0721> P2 Direction Register (P2DIR) <Address : H'0080 0722> P3 Direction Register (P3DIR) <Address : H'0080 0723>...
Page 210: Port Operation Mode Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers P0 Operation Mode Register (P0MOD) <Address: H'0080 0740> P00MOD P01MOD P02MOD P03MOD P04MOD P05MOD P06MOD P07MOD <When reset: H'00> Bit Name Function P00MOD 0: DB0 (Port P00 operation mode) 1: P00 P01MOD...
Page 211 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P1 Operation Mode Register (P1MOD) <Address: H'0080 0741> P10MOD P11MOD P12MOD P13MOD P14MOD P15MOD P16MOD P17MOD <When reset: H'00> Bit Name Function P10MOD 0: DB8 (Port P10 operation mode) 1: P10 P11MOD 0: DB9 (Port P11 operation mode)
Page 212 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P2 Operation Mode Register (P2MOD) <Address: H'0080 0742> P20MOD P21MOD P22MOD P23MOD P24MOD P25MOD P26MOD P27MOD <When reset: H'00> Bit Name Function P20MOD 0: A23 (Port P20 operation mode) 1: P20 P21MOD 0: A24 (Port P21 operation mode)
Page 213 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P3 Operation Mode Register (P3MOD) <Address: H'0080 0743> P30MOD P31MOD P32MOD P33MOD P34MOD P35MOD P36MOD P37MOD <When reset: H'00> Bit Name Function P30MOD 0: A15 (Port P30 operation mode) 1: P30 P31MOD 0: A16 (Port P31 operation mode)
Page 214 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P4 Operation Mode Register (P4MOD) <Address: H'0080 0744> P41MOD P42MOD P43MOD P44MOD P45MOD P47MOD <When reset: H'00> Bit Name Function No functions assigned – ____ ___ P41MOD 0: BLW/BLE (Port P41 operation mode) 1: P41 ____ ___ P42MOD...
Page 215 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset: H'00> Bit Name Function P70MOD 0: P70 (Port P70 operation mode) 1: BCLK/WR P71MOD 0: P71 ____...
Page 216 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P8 Operation Mode Register (P8MOD) <Address: H'0080 0748> P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD <When reset: H'00> Bit Name Function No functions assigned – P82MOD 0: P82 (Port P82 operation mode) 1: TXD0 P83MOD 0: P83...
Page 217 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P9 Operation Mode Register (P9MOD) <Address: H'0080 0749> P93MOD P94MOD P95MOD P96MOD <When reset: H'00> Bit Name Function 8-10 No functions assigned – P93MOD 0: P93 (Port P93 operation mode) 1: RXD3 P94MOD 0: P94...
Page 218 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P10 Operation Mode Register (P10MOD) <Address: H'0080 074A> P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD <When reset: H'00> Bit Name Function P100MOD 0: P100 (Port P100 operation mode) 1: TO8 P101MOD 0: P101 (Port P101 operation mode)
Page 219 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P11 Operation Mode Register (P11MOD) <Address: H'0080 074B> P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD <When reset: H'00> Bit Name Function P110MOD 0: P110 (Port P110 operation mode) 1: TO0 P111MOD 0: P111 (Port P111 operation mode)
Page 220 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P12 Operation Mode Register (P12MOD) <Address: H'0080 074C> P124MOD P125MOD P126MOD P127MOD <When reset: H'00> Bit Name Function No functions assigned – P124MOD 0: P124 (Port P124 operation mode) 1: TIN0A P125MOD 0: P125 (Port P125 operation mode)
Page 221 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P13 Operation Mode Register (P13MOD) <Address: H'0080 074D> P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD <When reset: H'00> Bit Name Function P130MOD 0: P130 (Port P130 operation mode) 1: TIN16/PWMOFF0 P131MOD 0: P131 (Port P131 operation mode)
Page 222 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P15 Operation Mode Register (P15MOD) <Address: H'0080 074F> P150MOD P153MOD <When reset: H'00> Bit Name Function P150MOD 0: P150 (Port P150 operation mode) 1: TIN8/TXD7 9,10 No functions assigned – P153MOD 0: P153 (Port P153 operation mode)
Page 223 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P17 Operation Mode Register (P17MOD) <Address: H'0080 0751> P172MOD P173MOD P174MOD P175MOD <When reset: H'00> Bit Name Function No functions assigned – P172MOD 0: P172 (Port P172 operation mode) 1: TIN10 P173MOD 0: P173 (Port P173 operation mode)
Page 224 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> P220MOD P225MOD <When reset: H'00> Bit Name Function P220MOD 0: P220 (Port P220 operation mode) 1: CTX0 No functions assigned – P225MOD 0: P225 (Port P225 operation mode) 1: use inhibited...
Page 225 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P4 Peripheral Output Select Register (P4SMOD) <Address: H'0080 0764> P46SMOD <When reset: H'00> Bit Name Function No functions assigned – P46SMOD 0:A13 _______ (Selects port P46 peripheral output) 1:CS3 No functions assigned –...
Page 226 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P7 Peripheral Output Select Register (P7SMOD) <Address: H'0080 0767> P73SMOD <When reset: H'00> Bit Name Function 8-10 No functions assigned – __________ P73SMOD 0: HACK (Selects port P73 peripheral output) 1: TXD3 12-15 No functions assigned...
Page 227 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P10-P11 Peripheral Output Select Register (P1011SMOD) <Address: H'0080 076A> P104 P105 P106 P107 P114 P115 P116 P117 SMOD SMOD SMOD SMOD SMOD SMOD SMOD SMOD <When reset: H'0000> Bit Name Function No functions assigned –...
Page 228 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P15 Peripheral Output Select Register (P15SMOD) <Address: H'0080 076F> P150SMOD P153SMOD <When reset: H'00> Bit Name Function P150SMOD 0: TIN8 (Port P150 operation mode) 1: TXD7 9,10 No functions assigned P153SMOD 0: TIN9 (Port P153 operation mode)
Page 229 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P22 Peripheral Output Select Register (P22SMOD) <Address: H'0080 0776> P225SMOD <When reset: H'00> Bit Name Function No functions assigned – P225SMOD 0: A12 (Selects port P225 peripheral output) 1: CS2 No functions assigned –...
Page 230 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Port Input Function Enable Register (PIEN) <Address: H'0080 0745> PIEN0 <When reset: H'00> Bit Name Function 8-14 No functions assigned – PIEN0 0: Disables input (to prevent current (Port input function enable bit) from flowing in) 1: Enables input This register is used to prevent electric current from flowing into the port input pin.
Page 231: Port Peripheral Circuits
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the ports on the microcomputer. P00 - P07(DB0 - DB7) Direction register P10 - P17(DB8 - DB15) P20 - P27(A23 - A30) P30 - P37(A15 - A22) Data bus...
Page 232 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P61 - P63 P225 Direction register Port output Data bus latch (DB0 - DB15) Input function enable Note 1: Although P46, P61-P63, and P225 serve as external bus interface control signal pins during external extended and processor modes, their functional description in this block diagram is omitted.
Page 233 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P72(HREQ) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register HREQ Input function enable P73(HACK/TXD3) Direction register P106(TO14/TXD4) P116(TO6/TXD5) Data bus Port output (DB0 - DB15) latch Operation mode register Peripheral function...
Page 234 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P84(SCLKI0,SCLKO0) P87(SCLKI1,SCLKO1) Direction register Data bus Port output latch (DB0 - DB15) Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function enable JTDI JTCK JTDI ,JTCK, JTMS JTMS...
Page 235 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P93(RXD3(/AD0IN8)) P124(TIN0A(/AD0IN9)) P125(TIN0B(/AD1IN9)) Data bus P126(TIN1A(/AD0IN10)) (DB0 - DB15) Operation mode P127(TIN1B(/AD1IN10)) register P132(TIN18(/AD0IN12)) P133(TIN19(/AD1IN12)) Peripheral function P134(TIN20(/AD0IN13)) input P135(TIN21(/AD1IN13)) P136(TIN22(/AD0IN14)) A-D input P137(TIN23(/AD1IN14)) P172(TIN10(/AD1IN9)) P173(TIN11(/AD1IN7)) Direction register Data bus Port output P95(RXD5(/AD1IN8)) latch (DB0 - DB15)
Page 236 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P100 - P103(TO8 - TO11) PWM output disable P110 - P113(TO0 - TO3) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register Peripheral function output Input function enable P104(TO12/SCLKI4) PWM output disable P114(TO4/SCLKI5)
Page 237 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P105(TO13/SCLKO4) PWM output disable P115(TO5/SCLKO5) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register Peripheral function output selector Peripheral function output 1 Peripheral function output 2 Input function enable P107(TO15/RXD4) Direction register P117(TO7/RXD5)
Page 238 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P153(TIN9/RXD7/AD1IN15) Direction register Data bus Port output (DB0 - DB15) latch Operation mode register Peripheral function input 1 Peripheral function input 2 Input function enable A-D input P130(TIN16/PWMOFF0/AD0IN11) P131(TIN17/PWMOFF1/AD1IN11) Data bus Operation mode (DB0 - DB15) register...
Page 239: Precautions On Input/Output Ports
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/Output Ports 8.5 Precautions on Input/Output Ports • When using ports in output mode Immediately after reset, the Port Data Register values are indeterminate.Therefore, write the initial output value to the Port Data Register before setting the Port Direction Register for output. Note that if the Port Direction Register is set for output before writing to the Port Data Register, an indeterminate value may be output for a while until the write data is set in the Port Data Register.
Page 240 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/Output Ports *** This is a blank page *** 8-40 Rev.1.0...
Page 241: Chapter 9 Dmac
CHAPTER 9 CHAPTER 9 DMAC 9.1 Outline of DMAC 9.2 DMAC Related Registers 9.3 Functional Description of DMAC 9.4 Precautions on Using DMAC...
Page 242 DMAC 9.1 Outline of DMAC 9.1 Outline of DMAC The microcomputer has 10-channel DMA (Direct Memory Access) Controller allowing data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs when triggered in software or by request from internal peripheral I/O.
Page 243 DMAC 9.1 Outline of DMAC DMA channel 0 Software start One DMA2 transfer completed Source address register A-D0 conversion completed Timer (TOM00_udf) All DMA1 transfers completed request Timer (TID0_udf,ovf) Destination address register selector Timer (TID1_udf,ovf) Timer (TIN16 input signal) PD module (TIN0A input signal) Serial I/O-2(transmit buffer empty) Transfer count register udf Serial I/O-7(transmit buffer empty)
Page 244 DMAC 9.1 Outline of DMAC DMA channel 5 Software start One DMA7 transfer completed All DMA0 transfers completed Source address register Serial I/O-2(reception completed) All DMA1 transfers completed Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) request Destination address register Timer (TIN16 input signal) selector PD module (TIN1A input signal) Timer (TOM16_udf)
Page 245 DMAC 9.2 DMAC Related Registers 9.2 DMAC Related Registers A memory map of DMA related registers is shown below. +0 address +1 address Address DMA0-4 Interrupt Request Status DMA0-4 Interrupt Mask Register H'0080 0400 Register (DM04ITST) (DM04ITMK) DMA5-9 Interrupt Request Status DMA5-9 Interrupt Mask Register H'0080 0408 Register (DM59ITST)
Page 246 DMAC 9.2 DMAC Related Registers +0 address +1 address Address DMA3 Channel Control Register DMA3 Transfer Count Register H’0080 0440 (DM3CNT) (DM3TCT) DMA3 Source Address Register (DM3SA) H’0080 0442 DMA3 Destination Address Register (DM3DA) H’0080 0444 DMA3 Request Extended Cause H’0080 0446 Register (DM3REQ) DMA8 Channel Control Register...
Page 247: Dma Channel Control Registers
DMAC 9.2 DMAC Related Registers 9.2.1 DMA Channel Control Registers DMA0 Channel Control Register (DM0CNT) <Address: H'0080 0410> MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 <When reset: H'00> Bit Name Function MDSEL0 0: Normal mode (Selects DMA0 transfer mode) 1: Ring buffer mode TREQF0 0: Not requested (DMA0 transfer request flag)
Page 248 DMAC 9.2 DMAC Related Registers DMA1 Channel Control Register (DM1CNT) <Address: H'0080 0420> MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 <When reset: H'00> Bit Name Function MDSEL1 0: Normal mode (Selects DMA1 transfer mode) 1: Ring buffer mode TREQF1 0: Not requested (DMA1 transfer request flag) 1: Requested 2, 3...
Page 249 DMAC 9.2 DMAC Related Registers DMA2 Channel Control Register (DM2CNT) <Address: H'0080 0430> MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 <When reset: H'00> Bit Name Function MDSEL2 0: Normal mode (Selects DMA2 transfer mode) 1: Ring buffer mode TREQF2 0: Not requested (DMA2 transfer request flag) 1: Requested 2, 3...
Page 250 DMAC 9.2 DMAC Related Registers DMA3 Channel Control Register (DM3CNT) <Address: H'0080 0440> MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 <When reset: H'00> Bit Name Function MDSEL3 0: Normal mode (Selects DMA3 transfer mode) 1: Ring buffer mode TREQF3 0: Not requested (DMA3 transfer request flag) 1: Requested 2, 3...
Page 251 DMAC 9.2 DMAC Related Registers DMA4 Channel Control Register (DM4CNT) <Address: H'0080 0450> MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 <When reset: H'00> Bit Name Function MDSEL4 0: Normal mode (Selects DMA4 transfer mode) 1: Ring buffer mode TREQF4 0: Not requested (DMA4 transfer request flag) 1: Requested 2, 3...
Page 252 DMAC 9.2 DMAC Related Registers DMA5 Channel Control Register (DM5CNT) <Address: H'0080 0418> MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 <When reset: H'00> Bit Name Function MDSEL5 0: Normal mode (Selects DMA5 transfer mode) 1: Ring buffer mode TREQF5 0: Not requested (DMA5 transfer request flag) 1: Requested 2, 3...
Page 253 DMAC 9.2 DMAC Related Registers DMA6 Channel Control Register (DM6CNT) <Address: H'0080 0428> MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 <When reset: H'00> Bit Name Function MDSEL6 0: Normal mode (Selects DMA6 transfer mode) 1: Ring buffer mode TREQF6 0: Not requested (DMA6 transfer request flag) 1: Requested 2, 3...
Page 254 DMAC 9.2 DMAC Related Registers DMA7 Channel Control Register (DM7CNT) <Address: H'0080 0438> MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 <When reset: H'00> Bit Name Function MDSEL7 0: Normal mode (Selects DMA7 transfer mode) 1: Ring buffer mode TREQF7 0: Not requested (DMA7 transfer request flag) 1: Requested 2, 3...
Page 255 DMAC 9.2 DMAC Related Registers DMA8 Channel Control Register (DM8CNT) <Address: H'0080 0448> MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 <When reset: H'00> Bit Name Function MDSEL8 0: Normal mode (Selects DMA8 transfer mode) 1: Ring buffer mode TREQF8 0: Not requested (DMA8 transfer request flag) 1: Requested 2, 3...
Page 256 DMAC 9.2 DMAC Related Registers DMA9 Channel Control Register (DM9CNT) <Address: H'0080 0458> MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 <When reset: H'00> Bit Name Function MDSEL9 0: Normal mode (Selects DMA9 transfer mode) 1: Ring buffer mode TREQF9 0: Not requested (DMA9 transfer request flag) 1: Requested 2, 3...
Page 257 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of a bit to select DMA transfer mode for each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable a DMA transfer, set the transfer size, and source/destination address directions.
Page 258: Dma Request Extended Cause Register
DMAC 9.2 DMAC Related Registers 9.2.2 DMA Request Extended Cause Register DMA0 Request Extended Cause Register (DM0REQ) <Address: H'0080 0416> REQESEL0 <When reset: H'00> Bit Name Function No functions assigned – REQESEL0 0000: All DMA1 transfers completed (Selects DMA0 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf...
Page 259 DMAC 9.2 DMAC Related Registers DMA1 Request Extended Cause Register (DM1REQ) <Address: H'0080 0426> REQESEL1 <When reset: H'00> Bit Name Function No functions assigned – REQESEL1 0000: All DMA1 transfers completed (Selects DMA1 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN17 input signal 0101: TOM02_udf...
Page 260 DMAC 9.2 DMAC Related Registers DMA2 Request Extended Cause Register (DM2REQ) <Address: H'0080 0436> REQESEL2 <When reset: H'00> Bit Name Function No functions assigned – REQESEL2 0000: All DMA1 transfers completed (Selects DMA2 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN18 input signal 0101: TOM07_udf...
Page 261 DMAC 9.2 DMAC Related Registers DMA3 Request Extended Cause Register (DM3REQ) <Address: H'0080 0446> REQESEL3 <When reset: H'00> Bit Name Function No functions assigned – REQESEL3 0000: All DMA1 transfers completed (Selects DMA3 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN19 input signal 0101: TOM03_udf...
Page 262 DMAC 9.2 DMAC Related Registers DMA4 Request Extended Cause Register (DM4REQ) <Address: H'0080 0456> REQESEL4 <When reset: H'00> Bit Name Function No functions assigned – REQESEL4 0000: All DMA1 transfers completed (Selects DMA4 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN23 input signal 0101: TOM04_udf...
Page 263 DMAC 9.2 DMAC Related Registers DMA5 Request Extended Cause Register (DM5REQ) <Address: H'0080 041E> REQESEL5 <When reset: H'00> Bit Name Function No functions assigned – REQESEL5 0000: All DMA1 transfers completed (Selects DMA5 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN1A input signal 0101: TOM16_udf...
Page 264 DMAC 9.2 DMAC Related Registers DMA6 Request Extended Cause Register (DM6REQ) <Address: H'0080 042E> REQESEL6 <When reset: H'00> Bit Name Function No functions assigned – REQESEL6 0000: All DMA1 transfers completed (Selects DMA6 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN20 input signal 0101: TOM05_udf...
Page 265 DMAC 9.2 DMAC Related Registers DMA7 Request Extended Cause Register (DM7REQ) <Address: H'0080 043E> REQESEL7 <When reset: H'00> Bit Name Function No functions assigned – REQESEL7 0000: All DMA1 transfers completed (Selects DMA7 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN1B input signal 0101: TOM06_udf...
Page 266 DMAC 9.2 DMAC Related Registers DMA8 Request Extended Cause Register (DM8REQ) <Address: H'0080 044E> REQESEL8 <When reset: H'00> Bit Name Function No functions assigned – REQESEL8 0000: All DMA1 transfers completed (Selects DMA8 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN21 input signal 0101: TOM17_udf...
Page 267 DMAC 9.2 DMAC Related Registers DMA9 Request Extended Cause Register (DM9REQ) <Address: H'0080 045E> REQESEL9 <When reset: H'00> Bit Name Function No functions assigned – REQESEL9 0000: All DMA1 transfers completed (Selects DMA9 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN22 input signal 0101: TOM10_udf...
Page 268 DMAC 9.2 DMAC Related Registers The DMA Request Extended Source Register is used to select a DMA transfer request extended source when "Extended request source" has been selected with the DMA Channel Control Register's cause of DMA request select (REQSLn) bits. (1) REQESELn (DMAn request extended source select) bits (D4-D7) These bits select a DMA transfer request extended source for each DMA channel.
Page 269: Dma Software Request Generation Registers
DMAC 9.2 DMAC Related Registers 9.2.3 DMA Software Request Generation Registers DMA0 Software Request Generation Registers (DM0SRI) <Address: H'0080 0460> DMA1 Software Request Generation Registers (DM1SRI) <Address: H'0080 0462> DMA2 Software Request Generation Registers (DM2SRI) <Address: H'0080 0464> DMA3 Software Request Generation Registers (DM3SRI) <Address: H'0080 0466>...
Page 270: Dma Source Address Registers
DMAC 9.2 DMAC Related Registers 9.2.4 DMA Source Address Registers DMA0 Source Address Registers (DM0SA) <Address: H'0080 0412> DMA1 Source Address Registers (DM1SA) <Address: H'0080 0422> DMA2 Source Address Registers (DM2SA) <Address: H'0080 0432> DMA3 Source Address Registers (DM3SA) <Address: H'0080 0442> DMA4 Source Address Registers (DM4SA) <Address: H'0080 0452>...
Page 271: Dma Destination Address Registers
DMAC 9.2 DMAC Related Registers 9.2.5 DMA Destination Address Registers DMA0 Destination Address Registers (DM0DA) <Address: H'0080 0414> DMA1 Destination Address Registers (DM1DA) <Address: H'0080 0424> DMA2 Destination Address Registers (DM2DA) <Address: H'0080 0434> DMA3 Destination Address Registers (DM3DA) <Address: H'0080 0444> DMA4 Destination Address Registers (DM4DA) <Address: H'0080 0454>...
Page 272: Dma Transfer Count Registers
DMAC 9.2 DMAC Related Registers 9.2.6 DMA Transfer Count Registers DMA0 Transfer Count Registers (DM0TCT) <Address: H'0080 0411> DMA1 Transfer Count Registers (DM1TCT) <Address: H'0080 0421> DMA2 Transfer Count Registers (DM2TCT) <Address: H'0080 0431> DMA3 Transfer Count Registers (DM3TCT) <Address: H'0080 0441> DMA4 Transfer Count Registers (DM4TCT) <Address: H'0080 0451>...
Page 273: Dma Interrupt Request Status Registers
DMAC 9.2 DMAC Related Registers 9.2.7 DMA Interrupt Request Status Registers DMA0-4 Interrupt Request Status Register (DM04ITST) <Address: H'0080 0400> DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 <When reset: H'00> Bit Name Function No functions assigned – DMITST4 0: No interrupt requested (DMA4 interrupt request status) 1: Interrupt requested DMITST3...
Page 274 DMAC 9.2 DMAC Related Registers DMA5-9 Interrupt Request Status Register (DM59ITST) <Address: H'0080 0408> DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 <When reset: H'00> Bit Name Function No functions assigned – DMITST9 0: No interrupt requested (DMA9 interrupt request status) 1: Interrupt requested DMITST8 (DMA8 interrupt request status) DMITST7...
Page 275: Dma Interrupt Mask Registers
DMAC 9.2 DMAC Related Registers 9.2.8 DMA Interrupt Mask Registers DMA0-4 Interrupt Mask Register (DM04ITMK) <Address: H'0080 0401> DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 <When reset: H'00> Bit Name Function 8-10 No functions assigned – DMITMK4 0: Enables interrupt request (DMA4 interrupt request mask) 1: Masks (disables) interrupt request DMITMK3 (DMA3 interrupt request mask)
Page 276 DMAC 9.2 DMAC Related Registers DMA5-9 Interrupt Mask Register (DM59ITMK) <Address: H'0080 0409> DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 <When reset: H'00> Bit Name Function 8-10 No functions assigned – DMITMK9 0: Enables interrupt request (DMA9 interrupt request mask) 1: Masks (disables) interrupt request DMITMK8 (DMA8 interrupt request mask) DMITMK7...
Page 277 DMAC 9.2 DMAC Related Registers DM04ITST <H'0080 0400> DM04ITMK <H'0080 0401> DMA4UDF Data bus 5-source inputs DMITST4 DMA transfer interrupt 0 DMITMK4 (Level) DMA3UDF DMITST3 DMITMK3 DMA2UDF DMITST2 DMITMK2 DMA1UDF DMITST1 DMITMK1 DMA0UDF DMITST0 DMITMK0 Figure 9.2.14 Block Diagram of DMA Transfer Interrupt 0 9-37 Rev.1.0...
Page 278 DMAC 9.2 DMAC Related Registers Figure 9.2.15 Block Diagram of DMA Transfer Interrupt 1 9-38 Rev.1.0...
Page 279: Functional Description Of Dmac
DMAC 9.3 Functional Description of DMAC 9.3 Functional Description of DMAC 9.3.1 Cause of DMA Request A DMA transfer can be requested individually for each DMA channel (0-9 channels) from multiple sources. There are various causes of DMA transfer request, so that a DMA transfer may be started by an internal peripheral I/O, started in software by a program, or started by completion of one or all DMA transfers on another channel (cascade mode).
Page 280 DMAC 9.3 Functional Description of DMAC Table 9.3.3 Causes of DMA Request on DMA1 and the Timing at Which Requests are Generated REQSL1 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA1 Software Request Generation Register Extended request cause –...
Page 281 DMAC 9.3 Functional Description of DMAC Table 9.3.5 Causes of DMA Request on DMA2 and the Timing at Which Requests are Generated REQSL2 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA2 Software Request Generation Register Extended request cause –...
Page 282 DMAC 9.3 Functional Description of DMAC Table 9.3.7 Causes of DMA Request on DMA3 and the Timing at Which Requests are Generated REQSL3 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA3 Software Request Generation Register Serial I/O-0 When serial I/O-0 transmit buffer is empty...
Page 283 DMAC 9.3 Functional Description of DMAC Table 9.3.9 Causes of DMA Request on DMA4 and the Timing at Which Requests are Generated REQSL4 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA4 Software Request Generation Register One DMA3 transfer completed When one transfer on DMA3 is completed (cascade mode)
Page 284 DMAC 9.3 Functional Description of DMAC Table 9.3.11 Causes of DMA Request on DMA5 and the Timing at Which Requests are Generated REQSL5 Causes of DMA Request DMA Request Generation Timing Software start or When any data is written to the DMA5 Software Request One DMA7 transfer completed Generation Register (software start) or one transfer on DMA7 is completed (cascade mode)
Page 285 DMAC 9.3 Functional Description of DMAC Table 9.3.13 Causes of DMA Request on DMA6 and the Timing at Which Requests are Generated REQSL6 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA6 Software Request Generation Register Serial I/O-1 When serial I/O-1 transmit buffer is empty...
Page 286 DMAC 9.3 Functional Description of DMAC Table 9.3.15 Causes of DMA Request on DMA7 and the Timing at Which Requests are Generated REQSL7 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA7 Software Request Generation Register Serial I/O-2 When serial I/O-2 transmit buffer is empty...
Page 287 DMAC 9.3 Functional Description of DMAC Table 9.3.17 Causes of DMA Request on DMA8 and the Timing at Which Requests are Generated REQSL8 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA8 Software Request Generation Register All DMA3 transfers completed When all transfers on DMA3 are completed (cascade mode)
Page 288 DMAC 9.3 Functional Description of DMAC Table 9.3.19 Causes of DMA Request on DMA9 and the Timing at Which Requests are Generated REQSL9 Causes of DMA Request DMA Request Generation Timing Software start When any data is written to the DMA9 Software Request Generation Register Serial I/O-3 When serial I/O-3 transmit buffer is empty...
Page 289: Dma Transfer Processing Procedure
DMAC 9.3 Functional Description of DMAC 9.3.2 DMA Transfer Processing Procedure The following explains how DMA transfers are performed by using DAM channel 0 as an example. Start DMA transfer processing Interrupt controller related Set Interrupt Controller DMA0-4 • Interrupt priority level register settings Interrupt Control Register •...
Page 290: Starting Dma
DMAC 9.3 Functional Description of DMAC 9.3.3 Starting DMA Use the REQSL (cause of DMA request select) bits to select the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. A DMA transfer starts when the selected cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1.
Page 291: Gaining And Releasing Control Of The Internal Bus
DMAC 9.3 Functional Description of DMAC 9.3.5 Gaining and Releasing Control of the Internal Bus Gaining and releasing control of the internal bus is arbitrated by a single-transfer method DMA on all channels. With the single-transfer method DMA, the DMA controller gains control of the internal bus when a DMA transfer request is accepted and returns bus control to the CPU after executing one session of DMA transfer (one read cycle + one write cycle of the internal peripheral clock).
Page 292: Address Space
DMAC 9.3 Functional Description of DMAC 9.3.8 Address Space The address space in which DMA transfers can be performed is 64 Kbytes (H'0080 0000 to H'0080 FFFF) of internal peripheral I/O or RAM for both source and destination. The source and destination addresses on each channel are set using the DMA Source Address and DMA Destination Address Registers.
Page 293 DMAC 9.3 Functional Description of DMAC (5) Transfer count value The transfer count value is decremented by one for each DMA transfer performed, regardless of whether the transfer unit is 8 or 16 bits. (6) Transfer byte position When the transfer unit = 8 bits, the LSB of the address register is effective for both the source and destination.
Page 294 DMAC 9.3 Functional Description of DMAC (7) Ring buffer mode When ring buffer mode is selected, operation starts from the transfer start address and when transferred 32 times, returns to the transfer start address again, from which transfer operation restarts. However, the 5 low-order bits of the ring buffer start address must always be B'00000. The following describes how the addresses are incremented in ring buffer mode.
Page 295: End Of Dma And Interrupt
DMAC 9.3 Functional Description of DMAC 9.3.10 End of DMA and Interrupt In normal mode, a DMA transfer ends when the transfer count register underflows after reaching the terminal count. When a transfer ends, the transfer enable bit is cleared to 0 to disable transfers. Also an interrupt request is generated at completion of a transfer.
Page 296: Precautions On Using Dmac
DMAC 9.4 Precautions on Using DMAC 9.4 Precautions on Using DMAC • About writing to the DMA related registers In DMA transfers, data are exchanged via the internal bus. Therefore, make sure the DMA related registers basically are written to immediately after reset or when transfers are disabled (transfer enable bit = 0).
Page 297 DMAC 9.4 Precautions on Using DMAC • Operating on DMA related registers by a DMA transfer When operating on DMA related registers using a DMA transfer (e.g., reloading the DMA related registers with their initial values by a DMA transfer), do not write to any DMA related registers on the local channel, i.e., the channel on which the DMA transfer is being performed.
Page 298 DMAC 9.4 Precautions on Using DMAC *** This is a blank page *** 9-58 Rev.1.0...
Page 299 CHAPTER 10 CHAPTER 10 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers 10.2 Common Timer Unit 10.3 TMS (Input Related 16-bit Timers) 10.4 TML (Input Related 32-bit Timers) 10.5 TID (Input Related 16-bit Timers) 10.6 TOM (Output Related 16-bit Timers)
Page 300: Outline Of The Input/Output Timers
INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers 10.1 Outline of the Input/Output Timers The 32172/32173 has four types of input/output timers, providing a total of 26 channels of timers. Table 10.1.1 Outline of Timers Name Type No. of Channels...
Page 301 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers Table 10.1.2 Interrupt Generating Functions of Timers Signal Name Timer Interrupt Request Source Input to Interrupt Controller (ICU) ICU Cause Input IRQ30 PWMOFF0, PWMOFF1 inputs PWM off input interrupt IRQ28 TIN8, TIN9 inputs Timer input interrupt 5 IRQ27 TIN10, TIN11 inputs...
Page 302 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers Table 10.1.4 A-D Conversion Start Request Functions of Timers Signal Name A-D Conversion Start Request Source A-D Converter AD0TRG TIN16 input, TOM0_6 underflow, Can be input for A-D0 conversion start trigger or TOM0 enable event AD1TRG TIN16 input, TOM0_6 underflow, Can be input for A-D1 conversion start trigger...
Page 303 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers IRQ30 PWM Output Disable PWMOFF0S TIN16/PWMOFF0 Control Register 0 IRQ21 TOM0_0 F/F0 DRQ2 IRQ21 TOM0_1 F/F1 DRQ3 IRQ21 TOM0_2 F/F2 DRQ4 IRQ21 F/F3 TOM0_3 I/2 Internal DRQ5 Peripheral PRS2 IRQ21 Clock TOM0_4 F/F4 DRQ6 IRQ21...
Page 304 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers I/2 Internal TMS0 Peripheral PRS0 IRQ19 cap3 cap2 cap1 cap0 Clock IRQ23 To A-D0, 1 Converter TIN16/PWMOFF0 TIN16S or PD Module DRQ13 IRQ23 TIN16S1 IRQ23 TIN17S TIN17/PWMOFF1 DRQ14 IRQ22 TIN18 TIN18S DRQ15 IRQ22 TIN18S1 IRQ22...
Page 305 INPUT/OUTPUT TIMERS 10.1 Outline of the Input/Output Timers TID0_udf,ovf TID1_udf,ovf TIN16 DMAIRQ0 DMA0 AD0 finished TIN0A SIO2-TXD TOM00_udf SIO7-TXD DMAIRQ0 DMA1 TOM01_udf TIN17 TOM02_udf SIO4-RXD PD_CMP0 PD_CMP1 DMAIRQ0 DMA2 TIN0B TIN18 TOM07_udf SIO5-RXD DMAIRQ0 SIO0-TXD DMA3 TIN19 SIO1-RXD TOM03_udf AD1 finished DMAIRQ0 DMA4 SIO0-RXD...
Page 306: Common Timer Unit
INPUT/OUTPUT TIMERS 10.2 Common Timer Unit 10.2 Common Timer Unit The common timer unit includes the following blocks: • Prescaler unit • Input processing control unit • Output flip-flop control unit • Interrupt control unit 10.2.1 Register Map of the Common Timer Unit The next page shows a register map of the common timer unit.
Page 307 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit Address +0 address +1 address TIN Input Processing Control TIN Input Processing Control H'0080 0800 Register0 (TINCR0) Register1 (TINCR1) TIN Input Processing Control TIN Input Processing Control H'0080 0802 Register2 (TINCR2) Register3 (TINCR3) TIN Input Processing Control TIN Input Processing Control H'0080 0804 Register4 (TINCR4)
Page 308: Prescaler Unit
INPUT/OUTPUT TIMERS 10.2 Common Timer Unit 10.2.2 Prescaler Unit The prescalers PRS0-3 are 8-bit counter, which generates clocks supplied to each timer (TMS, TML, TID, and TOM) from the divided-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripherals are operating at 20 MHz). The value of each prescaler register is initialized to H'00 when reset.
Page 309: Input Processing Control Unit
INPUT/OUTPUT TIMERS 10.2 Common Timer Unit 10.2.3 Input Processing Control Unit The input processing control unit performs TIN signal input processing. In its TIN input processing unit, this unit selects the active signal edge (rising or falling edge or both edges) or the active level (high or low) at which to generate the signal to be fed to each timer for the enable, measurement, and count source signals.
Page 310 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit Functions of TIN Input Processing Control Registers Item Function Rising edge Internal edge signal Falling edge Internal edge signal Both edges Internal edge signal Low level Internal level signal High level Internal level signal 10-12 Rev.1.0...
Page 311 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 0 (TINCR0) <Address: H'0080 0800> TIN21S TIN20S1 TIN20S <When reset: H'00> Bit Name Function No functions assigned – TIN21S 00: Ignores input (Selects TIN21 input processing) 01: Rising edge 10: Falling edge 11: Both edges TIN20S1...
Page 312 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 1 (TINCR1) <Address: H'0080 0801> TIN23S TIN22S1 TIN22S <When reset: H'00> Bit Name Function No functions assigned – 10,11 TIN23S 00: Ignores input (Selects TIN23 input processing) 01: Rising edge 10: Falling edge 11: Both edges 12,13...
Page 313 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 2 (TINCR2) <Address: H'0080 0802> TIN17S TIN16S1 TIN16S <When reset: H'00> Bit Name Function No functions assigned – TIN17S 00: Ignores input (Selects TIN17 input processing) 01: Rising edge 10: Falling edge 11: Both edges TIN16S1...
Page 314 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 3 (TINCR3) <Address: H'0080 0803> TIN19S TIN18S1 TIN18S <When reset: H'00> Bit Name Function No functions assigned – 10,11 TIN19S 00: Ignores input (Selects TIN19 input processing) 01: Rising edge 10: Falling edge 11: Both edges 12,13...
Page 315 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 4 (TINCR4) <Address: H'0080 0804> TIN17S2P TIN17S2 TIN16S2P TIN16S2 <When reset: H'00> Bit Name Function TIN17S2P – (Controls TIN17S2 write) TIN17S2 000: Ignores input (Selects TIN17 "PWMOFF1") 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level...
Page 316 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit • Set the TINCR4 Register TIN17S2P bit to 1 If a write cycle for any other area occurs within this interval, no data are set in the TIN17S2 bits. • Set the TINCR4 Register TIN17S2P bit to 0 Note: The data that is set here may be •...
Page 317 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Input Processing Control Register 5 (TINCR5) <Address: H'0080 0805> TIN11S TIN10S TIN9S TIN8S <When reset: H'00> Bit Name Function TIN11S 00: Ignores input (Selects TIN11 input processing) 01: Rising edge 10: Falling edge 11: Both edges 10,11 TIN10S...
Page 318: Output Flip-Flop Control Unit
INPUT/OUTPUT TIMERS 10.2 Common Timer Unit 10.2.4 Output Flip-flop Control Unit The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. There are following output flip-flop control registers. • F/F Protect Register 0 (FFP0) • F/F Protect Register 1 (FFP1) •...
Page 319 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit Port Operation Mode Register (PnMOD) TOM_udf F/Fn Output Data (FDn) Output Control (ON/OFF) F/F Protect (FPn) Note: Dn denotes the data bus. Figure 10.2.4 Configuration of the F/F Output Circuit 10-21 Rev.1.0...
Page 320 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit F/F Protect Register 0 (FFP0) <Address: H'0080 0CD5> <When reset: H'00> Bit Name Function FP0 (F/F0 protect) 0: Enables write to F/F output bit FP1 (F/F1 protect) 1: Disables write to F/F output bit FP2 (F/F2 protect) FP3 (F/F3 protect) FP4 (F/F4 protect)
Page 321 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit F/F Data Register 0 (FFD0) <Address: H'0080 0CD7> <When reset: H'00> Bit Name Function FD0 (F/F0 output data) 0: F/F output data = 0 FD1 (F/F1 output data) 1: F/F output data=1 FD2 (F/F2 output data) FD3 (F/F3 output data) FD4 (F/F4 output data) FD5 (F/F5 output data)
Page 322: Interrupt Control Unit
INPUT/OUTPUT TIMERS 10.2 Common Timer Unit 10.2.5 Interrupt Control Unit The interrupt control unit controls the interrupt signals output to the Interrupt Controller by each timer. There are following 11 timer interrupt control registers for each timer. • TIN Interrupt Control Register 0 (TINIR0) •...
Page 323 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit For interrupts which have two or more interrupt sources for one interrupt vector table, the interrupt control registers are used to control their interrupt requests and determine interrupt inputs. For this reason, the status flags in the Interrupt Controller only serve as the bits to determine whether interrupts are requested from the sources that have been enabled for interrupt and cannot be accessed for write.
Page 324 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit Example for clearing interrupt status Interrupt status flag Initial state Interrupt request b6 event occurs b4 event occurs Write to interrupt status Only b6 is cleared b4 retains data Figure 10.2.6 Example for Clearing Interrupt Status 10-26 Rev.1.0...
Page 325 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit The table below shows the relationship between the interrupt signals generated by the input/output timers and the inputs to the Interrupt Controller. Table 10.2.2 Interrupt Signals Generated by Timers Signal Name Generating Source Interrupt Input Source to ICU (Note1) Number of Input Sources IRQ20 TOM1_0 - TOM1_7...
Page 326 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 0 (TINIST0) <Address: H'0080 0840> TIN21IS TIN20IS1 TIN20IS <When reset: H'00> Bit Name Function No functions assigned – TIN21IS (TIN21 interrupt status) 0: Interrupt not requested TIN20IS1 1: Interrupt requested (TML measure 2 input detection interrupt status) TIN20IS (TIN20 interrupt status) W= : Only writing 0 is effective.
Page 327 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TINIST0 <H'0080 0840> TINIMA0 <H'0080 0841> TIN21edge 3-source inputs Data bus TIN21IS Timer input interrupt 3 (Level) IRQ25 TIN21IM TIN20edge TIN20IS1 TIN20IM1 TIN20edge TIN20IS TIN20IM Figure 10.2.7 Block Diagram of Timer Input Interrupt 3 10-29 Rev.1.0...
Page 328 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 1 (TINIST1) <Address: H'0080 0842> TIN23IS TIN22IS1 TIN22IS <When reset: H'00> Bit Name Function No functions assigned – TIN23IS (TIN23 interrupt status) 0: Interrupt not requested TIN22IS1 1: Interrupt requested (TML measure 0 input detection interrupt status) TIN22IS (TIN22 interrupt status) No functions assigned...
Page 329 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TINIST1 <H'0080 0842> TINIMA1 <H'0080 0843> TIN23edge Data bus 3-source inputs TIN23IS Timer input interrupt 2 (Level) IRQ24 TIN21IM TIN22edge TIN22IS1 TIN22IM1 TIN22edge TIN22IS TIN22IM Figure 10.2.8 Block Diagram of Timer Input Interrupt 2 10-31 Rev.1.0...
Page 330 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 2 (TINIST2) <Address: H'0080 0844> TIN17IS TIN16IS1 TIN16IS <When reset: H'00> Bit Name Function No functions assigned – TIN17IS (TIN17 interrupt status) 0: Interrupt not requested TIN16IS1 1: Interrupt requested (TMS measure 2 input detection interrupt status) TIN16IS (TIN16 interrupt status) W= : Only writing 0 is effective.
Page 331 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TINIST2 <H'0080 0844> TINIMA2 <H'0080 0845> TIN17edge Data bus 3-source inputs TIN17IS Timer input interrupt 1 (Level) IRQ23 TIN17IM TIN16edge TIN16IS1 TIN16IM1 TIN16edge TIN16IS TIN16IM Figure 10.2.9 Block Diagram of Timer Input Interrupt 1 10-33 Rev.1.0...
Page 332 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 3 (TINIST3) <Address: H'0080 0846> TIN19IS TIN18IS1 TIN18IS <When reset: H'00> Bit Name Function No functions assigned – TIN19IS (TIN19 interrupt status) 0: Interrupt not requested TIN18IS1 1: Interrupt requested (TMS measure 0 input detection interrupt status) TIN18IS (TIN22 interrupt status) No functions assigned...
Page 333 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TINIST3 <H'0080 0846> TINIMA3 <H'0080 0847> TIN19edge Data bus 3-source inputs TIN19IS Timer input interrupt 0 TIN19IM (Level) IRQ22 TIN18edge TIN18IS1 TIN18IM1 TIN18edge TIN18IS TIN18IM Figure 10.2.10 Block Diagram of Timer Input Interrupt 0 10-35 Rev.1.0...
Page 334 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 4 (TINIST4) <Address: H'0080 0848> TIN9IS TIN8IS <When reset: H'00> Bit Name Function No functions assigned – TIN9IS (TIN9 interrupt status) 0: Interrupt not requested TIN8IS (TIN8 interrupt status) 1: Interrupt requested W= : Only writing 0 is effective.
Page 335 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 5 (TINIST5) <Address: H'0080 084A> TIN11IS TIN10IS <When reset: H'00> Bit Name Function 0, 1 No functions assigned – TIN11IS (TIN11 interrupt status) 0: Interrupt not requested TIN10IS (TIN10 interrupt status) 1: Interrupt requested No functions assigned –...
Page 336 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TIN Interrupt Status Register 8 (TINIST8) <Address: H'0080 0850> PWOFIS1 PWOFIS0 <When reset: H'00> Bit Name Function No functions assigned – PWOFIS1 0: Interrupt not requested (PMW output disable interrupt status 1) 1: Interrupt requested PWOFIS0 (PMW output disable interrupt status 0) W= : Only writing 0 is effective.
Page 337 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TOM0 Interrupt Mask Register (TOM0IMA) <Address: H'0080 0CD2> TOM07IMA TOM06IMA TOM05IMA TOM04IMA TOM03IMA TOM02IMA TOM01IMA TOM00IMA <When reset: H'00> Bit Name Function TOM07IMA (TOM0_7 interrupt mask) 0: Enables interrupt request TOM06IMA (TOM0_6 interrupt mask) 1: Masks (disables) interrupt request TOM05IMA (TOM0_5 interrupt mask) TOM04IMA (TOM0_4 interrupt mask)
Page 338 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TOM0IMA <H'0080 0CD2> TOM0IST <H'0080 0CD3> TOM07udf Data bus TOM07IST TOM0 output interrupt TOM07IMA (Level) IRQ21 TOM06udf TOM06IST TOM06IMA TOM05udf TOM05IST TOM05IMA TOM04udf TOM04IST TOM04IMA TOM03udf TOM03IST TOM03IMA TOM02udf TOM02IST TOM02IMA TOM01udf TOM01IST TOM01IMA TOM00udf TOM00IST TOM00IMA...
Page 339 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TOM1 Interrupt Mask Register (TOM1IMA) <Address: H'0080 0DD2> TOM17IMA TOM16IMA TOM15IMA TOM14IMA TOM13IMA TOM12IMA TOM11IMA TOM10IMA <When reset: H'00> Bit Name Function TOM17IMA (TOM1_7 interrupt mask) 0: Enables interrupt request TOM16IMA (TOM1_6 interrupt mask) 1: Masks (disables) interrupt request TOM15IMA (TOM1_5 interrupt mask) TOM14IMA (TOM1_4 interrupt mask)
Page 340 INPUT/OUTPUT TIMERS 10.2 Common Timer Unit TOM1IMA <H'0080 0DD2> TOM1IST <H'0080 0DD3> TOM17udf Data bus TOM17IST TOM1 output interrupt IRQ20 TOM17IMA (Level) TOM16udf TOM16IST TOM16IMA TOM15udf TOM15IST TOM15IMA TOM14udf TOM14IST TOM14IMA TOM13udf TOM13IST TOM13IMA TOM12udf TOM12IST TOM12IMA TOM11udf TOM11IST TOM11IMA TOM10udf TOM10IST TOM10IMA...
Page 341: Tms (Input Related 16-Bit Timers)
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3 TMS (Input Related 16-bit Timers) 10.3.1 Outline of the TMS TMS (Timer Measure Small) consists of input related 16-bit timers allowing input pulses on four channels to be measured. Specifications of the TMS are listed below. A block diagram of the TMS is shown in the next page.
Page 342 INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) TMS 0 To TML0 IRQ19 1/2 internal peripheral Counter PRS0 Measure Register 3 clock (16-bit) IRQ23 Old Measure Register 3 To A-D0,1 and PD module TIN16 TIN16S cap3 Measure Register 2 IRQ23 DRQ13 TIN16S1 Old Measure Register 2...
Page 343: Tms Related Register Map
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.3 TMS Related Register Map A TMS related register map is shown below. Address +0 address +1 address H'0080 08E0 TMS0 Counter (TMS0CT) H'0080 08E2 TMS0 Measure 3 Register (TMS0MR3) H'0080 08E4 TMS0Measure 2 Register (TMS0MR2) H'0080 08E6 TMS0Measure 1 Register (TMS0MR1)
Page 344: Tms Control Register
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.4 TMS Control Register The TMS control register is used to select a TMS0 input event and controls TMS and TML counter startup. Following TMS control registers are included. • TMS0 Control Register (TMS0CR) TMS0 Control Register (TMS0CR) <Address: H'0080 08EA>...
Page 345: Tms Counter (Tms0Ct)
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.5 TMS Counter (TMS0CT) TMS0 Counter (TMS0CT) <Address: H'0080 08E0> TMS0CT <When reset: indeterminate> Bit Name Function 0-15 TMS0CT 16-bit counter value Note: This register must always be accessed in halfwords. The TMS counter is a 16-bit up-counter, which starts counting when the timer is activated (by writing to the enable bit in software).
Page 346: Tms Measure Registers (Tms0Mr3~0)
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.6 TMS Measure Registers (TMS0MR3-0) TMS0 Measure 3 Register (TMS0MR3) <Address: H'0080 08E2> TMS0 Measure 2 Register (TMS0MR2) <Address: H'0080 08E4> TMS0 Measure 1 Register (TMS0MR1) <Address: H'0080 08E6> TMS0 Measure 0 Register (TMS0MR0) <Address: H'0080 08E8>...
Page 347: Tms Old Measure Registers (Tms0Oldmr3~0)
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.7 TMS Old Measure Registers (TMS0OLDMR3-0) TMS0 Old Measure 3 Register (TMS0OLDMR3) <Address: H'0080 08F2> TMS0 Old Measure 2 Register (TMS0OLDMR2) <Address: H'0080 08F4> TMS0 Old Measure 1 Register (TMS0OLDMR1) <Address: H'0080 08F6> TMS0 Old Measure 0 Register (TMS0OLDMR0) <Address: H'0080 08F8>...
Page 348: Operation Of Tms Measure Input
INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) 10.3.8 Operation of TMS Measure Input (1) Outline of TMS measure input For TMS measure input, the counter first starts counting up when the timer is activated (by writing to the enable bit in software). Each time there is event input to TMS while the timer is operating, the values of the measure registers 0-3 are latched into the corresponding old measure registers 0-3 and the counter value is latched into the measure registers 0-3.
Page 349 INPUT/OUTPUT TIMERS 10.3 TMS (Input Related 16-bit Timers) (2) Precautions on using TMS measure input The following describes precautions to be observed when using TMS measure input. • If measure event input and write to the counter occur simultaneously in the same clock cycle, the write value is set in the counter and also latched into the measure register.
Page 350: Tml (Input Related 32-Bit Timers)
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4 TML (Input Related 32-bit Timers) 10.4.1 Outline of the TML TML (Timer Measure Large) consists of input related 32-bit timers allowing input pulses on four channels to be measured. Specifications of the TML are listed below. A block diagram of the TML is shown in the next page.
Page 351: Functional Outline Of The Tml
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) TML0 1/2 internal PRS0 To TMS0 peripheral clock Counter Measure register 3 PRS1 (32-bit) Old measure register 3 IRQ25 cap3 TIN20 TIN20S Measure register 2 DRQ17 IRQ25 TIN20S1 Old measure register 2 IRQ25 cap2 TIN21...
Page 352: Tml Related Register Map
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.3 TML Related Register Map A TML related register map is shown below. Address +0 address +1 address H'0080 0880 TML0 Counter, High (TML0CTH) H'0080 0882 TML0 Counter, Low (TML0CTL) TML0 Control Register Prescaler Register 1 H'0080 088A (TML0CR)
Page 353: Tml Control Register
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.4 TML Control Register TML0 Control Register (TML0CR) <Address: H'0080 088A> TML0SS0 TML0SS2 TML0CKS <When reset: H'00> Bit Name Function TML0SS0 0: External input TIN23 (Selects TML0 measure 0 source) 1: External input TIN22 No functions assigned –...
Page 354: Tml Counters
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.5 TML Counters TML0 Counter, High (TML0CTH) <Address: H'0080 0880> TML0 Counter, Low (TML0CTL) <Address: H'0080 0882> TML0CTH (16 high-order bits) TML0CTL (16 low-order bits) <When reset: indeterminate> Bit Name Function 0-15 TML0CTH 32-bit counter value (16 high-order bits) TML0CTL...
Page 355: Tml Measure Registers
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.6 TML Measure Registers TML0 Measure 3 Register (TML0MR3H) <Address: H'0080 0890> TML0 Measure 3 Register (TML0MR3L) <Address: H'0080 0892> TML0 Measure 2 Register (TML0MR2H) <Address: H'0080 0894> TML0 Measure 2 Register (TML0MR2L) <Address: H'0080 0896>...
Page 356: Tml Old Measure Registers
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.7 TML Old Measure Registers TML0 Old Measure 3 Register (TML0OLDMR3H) <Address: H'0080 08A0> TML0 Old Measure 3 Register (TML0OLDMR3L) <Address: H'0080 08A2> TML0 Old Measure 2 Register (TML0OLDMR2H) <Address: H'0080 08A4> TML0 Old Measure 2 Register (TML0OLDMR2L) <Address: H'0080 08A6>...
Page 357: Operation Of Tml Measure Input
INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) 10.4.8 Operation of TML Measure Input (1) Outline of TML measure input For TML measure input, the counter starts counting up when the timer is activated (by writing to the enable bit in software). Each time there is event input to the measure registers 0-3, the counter value is latched into the measure registers.
Page 358 INPUT/OUTPUT TIMERS 10.4 TML (Input Related 32-bit Timers) (2) Precautions on using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur simultaneously in the same clock cycle, the write value is set in the counter, whereas the up-count value (before rewriting) is latched into the measure register.
Page 359: Tid (Input Related 16-Bit Timers)
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5 TID (Input Related 16-bit Timers) 10.5.1 Outline of the TID TID (Timer Input Derivation) consists of input related 16-bit timers which can be operated in one of the following modes as selected in software: •...
Page 360 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) To TOM0_0-7 EN and A-D0TRG TID0 control circuits TIN8S IRQ28 To TOM1_0-7 EN control circuit CLK1 Reload register TIN8 DRQ0 IRQ28 Edge control TIN9S CLK2 TIN9 Up/down-counter IRQ18 1/2 internal peripheral PRS2 clock TOM0_0-7 To TOM0_0-7 EN and A-D0TRG...
Page 361: Tid Related Register Map
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5.2 TID Related Register Map A TID related register map is shown below. Address +0 address +1 address H'0080 0C8C TID0 Counter (TID0CT) H'0080 0C8E TID0 Reload Register (TID0RL) TID0 Control & Prescaler 2 H'0080 0CD0 Prescaler Register 2 (PRS2) Enable Register (TID0PRS2EN)
Page 362: Tid Control & Prescaler Enable Registers
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5.3 TID Control & Prescaler Enable Registers TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) <Address: H'0080 0CD1> TID0M TID0CEN TOM0ENS PRS2EN <When reset: H'00> Bit Name Function 8-10 TID0M X0X: Fixed period count mode (Selects TID0 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode...
Page 363 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) <Address: H'0080 0DD1> TID1M TID1CEN TOM1ENS PRS3EN <When reset: H'00> Bit Name Function 8-10 TID1M X0X: Fixed period count mode (Selects TID1 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode...
Page 364: Tid Counters (Tid0Ct And Tid1Ct)
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5.4 TID Counters (TID0CT and TID1CT) TID0 Counter (TID0CT) <Address: H'0080 0C8C> TID1 Counter (TID1CT) <Address: H'0080 0D8C> TID0CT , TID1CT <When reset: indeterminate> Bit Name Function 0-15 TID0CT,TID1CT 16-bit counter value Note: This register must always be accessed in halfwords.
Page 365: Tid Reload Registers (Tid0Rl And Tid1Rl)
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5.5 TID Reload Registers (TID0RL and TID1RL) TID0 Reload Register (TID0RL) <Address: H'0080 0C8E> TID1 Reload Register (TID1RL) <Address: H'0080 0D8E> TID0RL , TID1RL <When reset: indeterminate> Bit Name Function 0-15 TID0RL,TID1RL 16-bit reload register value Note: This register must always be accessed in halfwords.
Page 366: Outline Of Each Tid Operation Mode
INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) 10.5.6 Outline of Each TID Operation Mode The following outlines each TID operation mode. When using the TID, select one of these operation modes. (1) Fixed period count mode In fixed period count mode, the TID uses the reload register to generate an interrupt at intervals of the reload register set value + 1.
Page 367 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) (2) Event count mode In event count mode, the TID uses the signal (TIN8 or TIN10) entered from the outside as the clock source with which to run the counter. Note: TIN9 and TIN11 cannot be used as the clock source for the TID. By detecting the rising and falling edges of the externally sourced signal (TIN8 or TIN10), the TID generates a clock that is synchronized to the internal clock.
Page 368 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) (3) Multiply-by-4 event count mode In Multiply-by-4 event count mode, the TID uses two train of signals (TIN8 and TIN9, TIN10 and TIN11) entered from the outside as the clock sources with which to run the counter. The counter is switched between up-count and down-count by the input state of the two signals.
Page 369 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) TIN8 TIN9 Counter 7FFE 7FFF 8000 8001 8002 8003 8002 8001 8000 7FFF 7FFE value Switched over 8003 Counter 7FFE Up-count Down-count Figure 10.5.6 Up/Down Count Operation (Switchover Timing) TIN8 TIN9 Counter 7FFE 7FFF 8000...
Page 370 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) TIN8 TIN9 Counter FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF FFFE FFFD value Switched over FFFF Counter 0000 interrupt Up-count Down-count Figure 10.5.8 Up/Down Count Operation (Interrupt Timing) 10-72 Rev.1.0...
Page 371 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) (5) Up/down event count mode In up/down event count mode, the TID uses one of two train of signals (TIN8 or TIN10) entered from the outside as the clock source and the other (TIN9 or TIN11) as the up/down signal with which to run the counter.
Page 372 INPUT/OUTPUT TIMERS 10.5 TID (Input Related 16-bit Timers) TIN8 (TIN10) TIN9 (TIN11) Counter 0001 0002 0003 0002 0001 0000 FFFF FFFE FFFD FFFF 0000 FFFD FFFE value TID interrupt by overflow or underflow Figure 10.5.10 Up/Down Count Operation (Interrupt Timing) 10-74 Rev.1.0...
Page 373: Tom (Output Related 16-Bit Timers)
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6 TOM (Output Related 16-bit Timers) 10.6.1 Outline of the TOM TOM (Timer Output Modification) consists of output related 16-bit timers which can be run in one of the following modes as selected in software: <Output modes without correction function>...
Page 374 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) IRQ30 PWM output PWMOFF0 PWMOFF0S disable control register IRQ22 TOM0_0 F/F0 DRQ2 IRQ22 TOM0_1 F/F1 DRQ3 IRQ22 TOM0_2 F/F2 DRQ4 IRQ22 F/F3 TOM0_3 1/2 internal DRQ5 peripheral PRS2 IRQ22 clock TOM0_4 F/F4 DRQ6 IRQ22 F/F5...
Page 375: Outline Of Each Tom Operation Mode
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.2 Outline of Each TOM Operation Mode The following outlines each TOM operation mode. When using the TOM, select one of these operation modes. (1) PWM output mode (without correction function) In PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle.
Page 376 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (3) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle only once. When the timer is enabled after setting the initial value in the reload 0 and the reload 1 registers, the counter is loaded with the value of the reload 0 register synchronously with the count clock, from which it starts counting down.
Page 377: Tom Related Register Map
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.3 TOM Related Register Map A TOM related register map is shown below. Address +0 address +1 address PWM Output Disable Register 1 PWM Output Disable Register 0 H'0080 07A0 (PWMOFF1) (PWMOFF0) H'0080 07A2 PWM Output Disable Control PWM Output Disable Control...
Page 378 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) +0 address +1 address Address H’0080 0CC4 TOM0_6 Reload 1 Register (TOM06RL1) H’0080 0CC6 TOM0_6 Reload 0 Register (TOM06RL0) H’0080 0CC8 TOM0_7 Counter (TOM07CT) H’0080 0CCA H’0080 0CCC TOM0_7 Reload 1 Register (TOM07RL1) H’0080 0CCE TOM0_7 Reload 0 Register (TOM07RL0) Prescaler Register 2...
Page 379 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) +0 address +1 address Address H’0080 0DB4 TOM1_4 Reload 1 Register (TOM14RL1) H’0080 0DB6 TOM1_4 Reload 0 Register (TOM14RL0) H’0080 0DB8 TOM1_5 Counter (TOM15CT) H’0080 0DBA H’0080 0DBC TOM1_5 Reload 1 Register (TOM15RL1) H’0080 0DBE TOM1_5 Reload 0 Register (TOM15RL0) H’0080 0DC0...
Page 380: Pwm Output Disable Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.4 PWM Output Disable Registers PWM Output Disable Register 1 (PWMOFF1) <Address: H'0080 07A0> PWMOFF1P PWMOFF1S <When reset: H'00> Bit Name Function No functions assigned – PWMOFF1P (PWMOFF1S write control) PWMOFF1S 0: Enables output (Selects port P100-P105 output disable) 1: Disables output This register controls PWM outputs from TOM1_0 through TOM1_5 timers by enabling or disabling...
Page 381 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) PWM Output Disable Register 0 (PWMOFF0) <Address: H'0080 07A1> PWMOFF0P PWMOFF0S <When reset: H'00> Bit Name Function 8-13 No functions assigned – PWMOFF0P (PWMOFF0S write control) PWMOFF0S 0: Enables output (Selects port P110-P115 output disable) 1: Disables output This register controls PWM outputs from TOM0_0 through TOM0_5 timers by enabling or disabling PWM outputs on the corresponding ports P110-P115.
Page 382: Pwm Output Disable Control Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.5 PWM Output Disable Control Registers PWM Output Disable Control Register 1 (PLVCNT1) <Address: H'0080 07A4> PLVSEL1 PLVDIS1 <When reset: H'00> Bit Name Function No functions assigned – PLVSEL1 0: Selects to disable port output when low (Selects port P100-P105 output disable level) 1: Selects to disable port output when high PLVDIS1 0: Invalidates output disable selection...
Page 383 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (2) PLVDIS1 (port P100-P105 output disable selection validate/invalidate) bit (D7) This bit validates or invalidates the PWM output disable level selected with the PLVSEL1 bit. Setting this bit to 1 validates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output is disabled when the port P100-P105 is at the level selected with the PLVSEL1 bit.
Page 384 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) PWM Output Disable Control Register 0 (PLVCNT0) <Address: H'0080 07A5> PLVSEL0 PLVDIS0 <When reset: H'00> Bit Name Function 8-10 No functions assigned – PLVSEL0 0: Selects to disable port output when low (Selects port P110-P115 output disable level) 1: Selects to disable port output when high PLVDIS0 0: Invalidates output disable selection...
Page 385 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (2) PLVDIS0 (port P110-P115 output disable selection validate/invalidate) bit (D15) This bit validates or invalidates the PWM output disable level selected with the PLVSEL1 bit. Setting this bit to 1 validates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output is disabled when the port P110-P115 is at the level selected with the PLVSEL0 bit.
Page 386: Tom Control Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.6 TOM Control Registers TOM0 Control Register (TOM0CR) <Address: H'0080 0CDA> TOM00M TOM01M TOM02M TOM03M TOM04M TOM05M TOM06M TOM07M <When reset: H'0000> Bit Name Function TOM00M 00: Single-shot output mode (Selects TOM0_0 operation mode) 01: Single-shot PWM output mode TOM01M 10: Successive output mode...
Page 387 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1 Control Register (TOM1CR) <Address: H'0080 0DDA> TOM10M TOM11M TOM12M TOM13M TOM14M TOM15M TOM16M TOM17M <When reset: H'0000> Bit Name Function TOM10M 00: Single-shot output mode (Selects TOM1_0 operation mode) 01: Single-shot PWM output mode TOM11M 10: Successive output mode (Selects TOM1_1 operation mode)
Page 388: Tom Counters
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.7 TOM Counters TOM0_0 Counter (TOM00CT) <Address: H'0080 0C90> TOM0_1 Counter (TOM01CT) <Address: H'0080 0C98> TOM0_2 Counter (TOM02CT) <Address: H'0080 0CA0> TOM0_3 Counter (TOM03CT) <Address: H'0080 0CA8> TOM0_4 Counter (TOM04CT) <Address: H'0080 0CB0> TOM0_5 Counter (TOM05CT) <Address: H'0080 0CB8>...
Page 389 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1_0 Counter (TOM10CT) <Address: H'0080 0D90> TOM1_1 Counter (TOM11CT) <Address: H'0080 0D98> TOM1_2 Counter (TOM12CT) <Address: H'0080 0DA0> TOM1_3 Counter (TOM13CT) <Address: H'0080 0DA8> TOM1_4 Counter (TOM14CT) <Address: H'0080 0DB0> TOM1_5 Counter (TOM15CT) <Address: H'0080 0DB8>...
Page 390: Tom Reload 0 Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.8 TOM Reload 0 Registers TOM0_0 Reload 0 Register (TOM00RL0) <Address: H'0080 0C96> TOM0_1 Reload 0 Register (TOM01RL0) <Address: H'0080 0C9E> TOM0_2 Reload 0 Register (TOM02RL0) <Address: H'0080 0CA6> TOM0_3 Reload 0 Register (TOM03RL0) <Address: H'0080 0CAE>...
Page 391 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1_0 Reload 0 Register (TOM10RL0) <Address: H'0080 0D96> TOM1_1 Reload 0 Register (TOM11RL0) <Address: H'0080 0D9E> TOM1_2 Reload 0 Register (TOM12RL0) <Address: H'0080 0DA6> TOM1_3 Reload 0 Register (TOM13RL0) <Address: H'0080 0DAE> TOM1_4 Reload 0 Register (TOM14RL0) <Address: H'0080 0DB6>...
Page 392: Tom Reload 1 Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.9 TOM Reload 1 Registers TOM0_0 Reload 1 Register (TOM00RL1) <Address: H'0080 0C94> TOM0_1 Reload 1 Register (TOM01RL1) <Address: H'0080 0C9C> TOM0_2 Reload 1 Register (TOM02RL1) <Address: H'0080 0CA4> TOM0_3 Reload 1 Register (TOM03RL1) <Address: H'0080 0CAC>...
Page 393 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1_0 Reload 1 Register (TOM10RL1) <Address: H'0080 0D94> TOM1_1 Reload 1 Register (TOM11RL1) <Address: H'0080 0D9C> TOM1_2 Reload 1 Register (TOM12RL1) <Address: H'0080 0DA4> TOM1_3 Reload 1 Register (TOM13RL1) <Address: H'0080 0DAC> TOM1_4 Reload 1 Register (TOM14RL1) <Address: H'0080 0DB4>...
Page 394: Tom Enable Protect Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.10 TOM Enable Protect Registers TOM0 Enable Protect Register (TOM0PRO) <Address: H'0080 0CDD> TOM00PRO TOM01PRO TOM02PRO TOM03PRO TOM04PRO TOM05PRO TOM06PRO TOM07PRO <When reset: H'00> Bit Name Function TOM00PRO 0: Enables rewriting (TOM0_0 enable protect) 1: Disables rewriting TOM01PRO (TOM0_1 enable protect)
Page 395 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1 Enable Protect Register (TOM1PRO) <Address: H'0080 0DDD> TOM10PRO TOM11PRO TOM12PRO TOM13PRO TOM14PRO TOM15PRO TOM16PRO TOM17PRO <When reset: H'00> Bit Name Function TOM10PRO 0: Enables rewriting (TOM1_0 enable protect) 1: Disables rewriting TOM11PRO (TOM1_1 enable protect) TOM12PRO...
Page 396: Tom Count Enable Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.11 TOM Count Enable Registers TOM0 Count Enable Register (TOM0CEN) <Address: H'0080 0CDF> TOM00CEN TOM01CEN TOM02CEN TOM03CEN TOM04CEN TOM05CEN TOM06CEN TOM07CEN <When reset: H'00> Bit Name Function TOM00CEN 0: Stops counting (TOM0_0 count enable) 1: Enables counting TOM01CEN (TOM0_1 count enable)
Page 397 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM1 Count Enable Register (TOM1CEN) <Address: H'0080 0DDF> TOM10CEN TOM11CEN TOM12CEN TOM13CEN TOM14CEN TOM15CEN TOM16CEN TOM17CEN <When reset: H'00> Bit Name Function TOM10CEN 0: Stops counting (TOM1_0 count enable) 1: Enables counting TOM11CEN (TOM1_1 count enable) TOM12CEN...
Page 398: Tid Control & Prescaler Enable Registers
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.12 TID Control & Prescaler Enable Registers TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) <Address: H'0080 0CD1> TID0M TID0CEN TOM0ENS PRS2EN <When reset: H'00> Bit Name Function 8-10 TID0M X0X: Fixed period count mode (Selects TID0 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode...
Page 399 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN) <Address: H'0080 0DD1> TID1M TID1CEN TOM1ENS PRS3EN <When reset: H'00> Bit Name Function 8-10 TID1M X0X: Fixed period count mode (Selects TID1 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode...
Page 400 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) Selects TOM0 enable source (TOM0ENS) Selects TOM1 enable source Disables event enable (TOM1ENS) TID0 output EN-ON Disables event enable TOM0_7 output TID1 output External input TIN18 TOM0m enable TOM1_7 output External input TIN19 (TOM0mCEN) TOM0m enable control TID0 or TOM0_7 output...
Page 401: Operation Of Tom In Pwm Output Mode
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.13 Operation of TOM in PWM Output Mode (1) Outline of PWM Output Mode for TOM In PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle.
Page 402 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) Enabled (by writing to the enable Underflow Underflow bit or by external input) (first time) (second time) Count clock Enable bit Counts down from Counts down from Counts down from reload 0 register reload 1 register reload 0 register set value...
Page 403 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (2) Updating of TOM reload registers in PWM mode In PWM output mode, when the timer is idle, the reload 0 and reload 1 registers are updated simultaneously when data are written to the registers. However, when the timer is operating, the reload 1 register is updated by updating the reload 0 register.
Page 404 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (a) When updating of the reload registers takes effect in the current period (reflected in the next period) Write to reload 0 (reload 1 data latched) Write to reload 1 Reload 0 register H'1000 H'8000 Reload 1 register...
Page 405: Operation Of Tom In Single-Shot Output Mode
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.14 Operation of TOM in Single-shot Output Mode (without Correction Function) (1) Outline of single-shot output mode for TOM In single-shot output mode, the TOM generates a pulse in duration of the reload 0 register set value + 1 only once and then stops.
Page 406 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) Enabled (by writing to the enable bit Disabled or by external input) (by underflow) Count clock Enable bit H'FFFF Counts down from the reload 0 H'A000 register set value Counter H'0000 Reload 0 register H'A000 Reload 1 register (Unused)
Page 407: Operation Of Tom In Single-Shot Pwm Output Mode
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.15 Operation of TOM in Single-shot PWM Output Mode (without Correction Function) (1) Outline of single-shot PWM output mode for TOM In single-shot PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle only once.
Page 408: (Without Correction Function)
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) Enabled (by writing to the enable bit Underflow Underflow or by external input) (first time) (second time) Count clock Enable bit H'FFFF H'F000 H'EFFF Counts down from Counts down from reload 1 register reload 0 register H'A000 set value...
Page 409: Operation Of Tom In Successive Output Mode
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.16 Operation of TOM in Successive Output Mode (without Correction Function) (1) Outline of successive output mode for TOM In successive output mode, the counter counts down from its set value and upon underflowing, it is loaded with the value of the reload 0 register.
Page 410 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) Enabled (by writing to the enable bit Underflow Underflow or by external input) (first time) (second time) Count clock Enable bit H'FFFF H'DFFF H'DFFF H'E000 Counts down from Counts down from Counts down from the reload 0 register the reload 0 register the counter set value...
Page 411: Tom Output Disable Function
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.17 TOM Output Disable Function The TOM has the function to disable PWM outputs from TOM0_0-TOM0_5 and TOM1_0-TOM1_5 timers. The circuit configuration of this PWM output disable function is shown in Figure 10.6.15. There are following three methods to disable PWM outputs.
Page 412 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) (1) Disabling PWM outputs with the signal entered from the external pin (TIN16 or TIN17) The input signal on the external pin TIN16 may be used to disable PWM outputs of TOM0_0- TOM0_5 timers from being output to the corresponding ports P110-P115.
Page 413 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) • To disable PWM outputs using the port P110-P115 level Set the PLVCNT0 Register D14 bit (PLVSEL0) to 1 or 0 to select the port level (high or low) at which to disable PWM outputs. Set the PLVCNT0 Register D15 bit (PLVDIS0) to 1 (to validate output disable setting).
Page 414: Example For Using The Tom In Motor Control Applications
INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) 10.6.18 Example for Using the TOM in Motor Control Applications The microcomputer contains two blocks of TOM timers which are designed to reduce software load during motor control. This section explains an example for using TOM0 in motor control applications.
Page 415 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) TOM start 20KHz : Short-circuiting Delay Single shot prevention time TO0(U) Delay TO1(/U) Single shot TO2(V) TO3(/V) TO4(W) TO5(/W) Figure 10.6.18 Conceptual Diagram of Motor Control 10-117 Rev.1.0...
Page 416 INPUT/OUTPUT TIMERS 10.6 TOM (Output Related 16-bit Timers) *** This is a blank page *** 10-118 Rev.1.0...
Page 417: Chapter 11 A-D Converters
CHAPTER 11 CHAPTER 11 A-D CONVERTERS 11.1 Outline of the A-D Converters 11.2 A-D Converter Related Registers 11.3 Functional Description of the A-D Converters 11.4 Precautions on Using the A-D Converters...
Page 418: Conversion Modes
11.1 Outline of the A-D Converters 11.1 Outline of the A-D Converters The 32172/32173 contains two 10-bit resolution A-D converters based on successive approximation method (A-D0 and A-D1 Converters). The A-D0 Converter has eight channels of dedicated analog input pins (AD0IN0-AD0IN7) and eight other channels of analog input pins which are shared with input/output ports or internal peripheral I/O input/output pins (AD0IN8-AD0IN15), for a total of 16 channels.
Page 419 A-D CONVERTERS 11.1 Outline of the A-D Converters The A-D converters are outlined in Table 11.1.1. A block diagram of the A-D converters are shown in Figures 11.1.1 and 11.1.2, respectively. Table 11.1.1 Outline of the A-D Converters (1/2) Item Content Analog input 16 channels x 2...
Page 420 A-D CONVERTERS 11.1 Outline of the A-D Converters Table 11.1.2 Outline of the A-D Converters (2/2) Item Content 299 × 1/f(BCLK) Conversion speed During single Low speed mode Normal Double speed 173 × 1/f(BCLK) f(BCLK): mode 131 × 1/f(BCLK) Internal peripheral clock High speed mode Normal Double speed 89 ×...
Page 421 A-D CONVERTERS 11.1 Outline of the A-D Converters Internal data bus Read out in 8 bits Shifter Read out in 10 bits AD0DT0 10-bit A-D0 Data Register 0 AD0DT1 10-bit A-D0 Data Register 1 AD0SIM0,1 A-D0 Single Mode Register AD0DT2 10-bit A-D0 Data Register 2 AD0SCM0,1 A-D0 Scan Mode Register...
Page 422 A-D CONVERTERS 11.1 Outline of the A-D Converters Internal data bus Read out in 8 bits Shifter Read out in 10 bits AD1DT0 10-bit A-D1 Data Register 0 AD1DT1 AD1SIM0,1 10-bit A-D1 Data Register 1 A-D1 Single Mode Register AD1DT2 10-bit A-D1 Data Register 2 AD1SCM0,1 A-D1 Scan Mode Register...
Page 423 A-D CONVERTERS 11.1 Outline of the A-D Converters 11.1.1 Conversion Modes The A-D converters have two conversion modes: "A-D conversion mode" and "comparator mode." (1) A-D conversion mode In A-D conversion mode, the A-D converter converts the analog input voltage on a specified channel from analog to digital quantities.
Page 424 A-D CONVERTERS 11.1 Outline of the A-D Converters 11.1.2 Operation Modes The A-D converters have two operation modes: "single mode" and "scan mode." (1) Single mode In single mode, the A-D converter A-D converts or comparates the analog input voltage on one selected channel only once.
Page 425 A-D CONVERTERS 11.1 Outline of the A-D Converters (2) Scan mode In scan mode, the A-D converter sequentially A-D converts analog input voltages on specified channels (channel 0-15) selected with Scan Mode Register 1 scan loop select bits, beginning with the channel ADiIN0 (i = 0, 1). This mode further consists of "single-shot scan mode"...
Page 426 A-D CONVERTERS 11.1 Outline of the A-D Converters Table 11.1.2 A-D Conversion Result Storage Registers during Scan Mode Channels selected with Channels to be converted Channels to be converted A-D conversion result Scan Mode Register 1 in single-shot scan mode in continuous scan mode storage register B'0000 : 0...
Page 427 A-D CONVERTERS 11.1 Outline of the A-D Converters 11.1.3 Special Operation Modes (1) Forcibly execute single mode during scan mode operation In this special operation mode, the A-D converter forcibly executes single mode conversion (A-D conversion or comparate) on a specified channel while operating in scan mode. The conversion result is stored in the 10-bit A-D Data Register of the selected channel in the case of A-D conversion mode, or in the 10-bit A-D Comparate Data Register of the selected channel in the case of comparator mode.
Page 428 A-D CONVERTERS 11.1 Outline of the A-D Converters (2) Start scan mode after executing single mode In this special operation mode, the A-D converter starts scan operation from single mode conversion (A-D conversion or comparate) in succession. To start in software, select software trigger using the Scan Mode Register 0's A-D conversion start trigger select bit and set the said register's A-D conversion start bit to 1 while performing single mode conversion.
Page 429 A-D CONVERTERS 11.1 Outline of the A-D Converters (3) Restart conversion In this special operation mode, the A-D converter reexecutes single mode or scan mode operation from the beginning after stopping it while in progress. In the case of single mode, the operation being executed is reexecuted by setting Single Mode Register 0's A-D conversion start bit to 1 again or by entering a hardware trigger signal (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A-D0 Converter;...
Page 430: Interrupt And Dma Transfer Requests By A-D Converters
A-D CONVERTERS 11.1 Outline of the A-D Converters 11.1.4 Interrupt and DMA Transfer Requests by A-D Converters The A-D converter can generate an A-D conversion interrupt request or DMA transfer request when A-D conversion, comparate, or single-shot scan is finished or each time one cycle of continuous scan mode is finished.
Page 431: A-D Converter Related Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2 A-D Converter Related Registers An A-D converter related register map is shown below. Address +0 address +1 address A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 H’0080 0080 (AD0SIM0) (AD0SIM1) H’0080 0082 A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1...
Page 432 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 address +1 address 8-bit A-D0 Data Register H'0080 00D0 (AD08DT0) 8-bit A-D0 Data Register H'0080 00D2 (AD08DT1) 8-bit A-D0 Data Register H'0080 00D4 (AD08DT2) 8-bit A-D0 Data Register H'0080 00D6 (AD08DT3) 8-bit A-D0 Data Register H'0080 00D8 (AD08DT4)
Page 433 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 address +1 address A-D1 Single Mode Register 0 A-D1 Single Mode Register 1 H'0080 0A80 (AD1SIM0) (AD1SIM1) H'0080 0A82 A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 H'0080 0A84 (AD1SCM0) (AD1SCM1) A-D1 Conversion Speed Control Register...
Page 434 A-D CONVERTERS 11.2 A-D Converter Related Registers Address +0 address +1 address 8-bit A-D1 Data Register H'0080 0AD0 (AD18DT0) 8-bit A-D1 Data Register H'0080 0AD2 (AD18DT1) 8-bit A-D1 Data Register H'0080 0AD4 (AD18DT2) 8-bit A-D1 Data Register H'0080 0AD6 (AD18DT3) 8-bit A-D1 Data Register H'0080 0AD8 (AD18DT4)
Page 435: A-D Single Mode Registers 0
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.1 A-D Single Mode Registers 0 A-D0 Single Mode Register 0 (AD0SIM0) <Address: H'0080 0080> AD0STRG1 AD0STRG0 AD0SSEL AD0SREQ AD0SCMP AD0SSTP AD0SSTT <When reset: H'04> Bit Name Function AD0STRG1 (Note 1) Selects A-D0 hardware trigger (A-D0 hardware trigger select 1) with D0 and D2 bits D0 D2...
Page 436 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Single Mode Register 0 (AD1SIM0) <Address: H'0080 0A80> AD1STRG1 AD1STRG0 AD1SSEL AD1SREQ AD1SCMP AD1SSTP AD1SSTT <When reset: H'04> Bit Name Function AD1STRG1 (Note 1) Selects A-D1 hardware trigger (A-D1 hardware trigger select 1) with D0 and D2 bits D0 D2 0: TOM0_6 underflow...
Page 437 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnSTRG1 and ADnSTRG0 (A-Dn hardware trigger select) bits (D0, D2) When starting A-D conversion of the A-Dn converter in hardware, these bits select the cause for which to start conversion (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for A-D0;...
Page 438 A-D CONVERTERS 11.2 A-D Converter Related Registers If the A-Dn conversion start and A-Dn conversion stop bits are set to 1 simultaneously, the latter has priority so that the A-Dn conversion is stopped. If this bit is set to 1 while single mode operation in special mode "Forcibly execute single mode during scan mode operation"...
Page 439: A-D Single Mode Registers 1
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.2 A-D Single Mode Registers 1 A-D0 Single Mode Register 1 (AD0SIM1) <Address: H'0080 0081> AD0SMSL AD0SSPD AN0SEL <When reset: H'00> Bit Name Function AD0SMSL 0: A-D0 conversion mode (Select A-D0 conversion mode) 1: Comparator mode AD0SSPD (Note 1) 0: Normal...
Page 440 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Single Mode Register 1 (AD1SIM1) <Address: H'0080 0A81> AD1SMSL AD1SSPD AN1SEL <When reset: H'00> Bit Name Function AD1SMSL 0: A-D1 conversion mode (Select A-D1 conversion mode) 1: Comparator mode AD1SSPD (Note 1) 0: Normal (Select A-D1 conversion speed) 1: Double speed...
Page 441 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnSMSL (A-Dn conversion mode select) bit (D8) This bit selects A-D conversion mode when the A-Dn converter is operating in single mode. Setting this bit to 0 selects A-D conversion mode; setting this bit to 1 selects comparator mode. (2) ADnSSPD (A-Dn conversion speed select) bit (D9) This bit selects the A-D conversion speed when the A-Dn converter is operating in single mode.
Page 442: A-D Scan Mode Registers 0
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.3 A-D Scan Mode Registers 0 A-D0 Scan Mode Register 0 (AD0SCM0) <Address: H'0080 0084> AD0CTRG1 AD0CMSL AD0CTRG0 AD0CSEL AD0CREQ AD0CCMP AD0CSTP AD0CSTT <When reset: H'04> Bit Name Function AD0CTRG1 (Note 1) Selects A-D0 hardware trigger with (A-D0 hardware trigger select 1) D0 and D2 bits D0 D2...
Page 443 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Scan Mode Register 0 (AD1SCM0) <Address: H'0080 0A84> AD1CTRG1 AD1CMSL AD1CTRG0 AD1CSEL AD1CREQ AD1CCMP AD1CSTP AD1CSTT <When reset: H'04> Bit Name Function AD1CTRG1 (Note 1) Selects A-D1 hardware trigger with (A-D1 hardware trigger select 1) D0 and D2 bits D0 D2 0: TOM0_6 underflow...
Page 444 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnCTRG1 and ADnCTRG0 (A-Dn hardware trigger select) bits (D0, D2) When starting A-D conversion of the A-Dn converter in hardware, these bits select the cause for which to start conversion (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for A-D0;...
Page 445 A-D CONVERTERS 11.2 A-D Converter Related Registers (5) ADnCCMP (A-Dn conversion complete) bit (D5) This is a read-only bit, and is 1 when reset. This bit is 0 when scan mode conversion of the A-Dn converter is in progress and set to 1 when single-shot scan mode is completed or when continuous scan mode is stopped by setting the ADnCSTT (A-Dn conversion stop) bit to 1.
Page 446: A-D Scan Mode Registers 1
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.4 A-D Scan Mode Registers 1 A-D0 Scan Mode Register 1 (AD0SCM1) <Address: H'0080 0085> AD0CSPD AN0SCAN <When reset: H'00> Bit Name Function No functions assigned – AD0CSPD (Note 1) 0: Normal (Select A-D0 conversion speed) 1: Double speed 10,11 No functions assigned...
Page 447 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Scan Mode Register 1 (AD1SCM1) <Address: H'0080 0A85> AD1CSPD AN1SCAN <When reset: H'00> Bit Name Function No functions assigned – AD1CSPD (Note 1) 0: Normal (Select A-D1 conversion speed) 1: Double speed 10,11 No functions assigned –...
Page 448 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnCSPD (A-Dn conversion speed select) bit (D9) This bit selects the A-D conversion speed when the A-Dn converter is operating in scan mode. Setting this bit to 0 selects normal speed; setting this bit to 1 selects double speed. Note: Because the A-Dn conversion speed during scan mode is determined by a combined use of this ADnCSPD bit and the A-Dn Conversion Speed Control Register ADnCVSD bit, make sure the ADnCSPD and ADnCVSD bits both are set.
Page 449: A-D Conversion Speed Control Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.5 A-D Conversion Speed Control Registers A-D0 Conversion Speed Control Register (AD0CVSCR) <Address: H'0080 0087> AD0CVSD <When reset: H'00> Bit Name Function 8-14 No functions assigned – AD0CVSD (Note) 0: Low speed mode (Control A-D0 conversion seed) 1: High speed mode Note: The A-D0 conversion speed is determined by a combined use of this AD0CVSD bit and the A-D0...
Page 450 A-D CONVERTERS 11.2 A-D Converter Related Registers (1) ADnCSPD (A-Dn conversion speed select) bit (D15) This bit controls the A-D conversion speed of the A-Dn converter during single or scan mode. Setting this bit to 0 selects low speed mode; setting this bit to 1 selects high speed mode. Note: The A-Dn conversion speed is determined by a combined use of this ADnCVSD bit and the A-Dn Single Mode Register 1 ADnSSPD bit when operating in single mode, or a combined use of this ADnCVSD bit and the A-Dn Scan Mode Register 1 ADnCSPD bit...
Page 451: A-D Digital Input Control Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.6 A-D Digital Input Control Registers A-D0 Digital Input Control Register (AD0CHCON) <Address: H'0080 008E> AD0C AD0C AD0C AD0C AD0C AD0C AD0C AD0C H8CN H9CN H10CN H11CN H12CN H13CN H14CN H15CN <When reset: H'00> Bit Name Function No functions assigned (Note 1)
Page 452: A-D Successive Approximation Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.7 A-D Successive Approximation Registers A-D0 Successive Approximation Register (AD0SAR) <Address: H'0080 0088> AD0SAR <When reset: indeterminate> Bit Name Function No functions assigned – 6-15 AD0SAR • A-D0 successive approximation value (A-D0 successive approximation (A-D conversion mode) value/comparison value) •...
Page 453 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Successive Approximation Register (AD1SAR) <Address: H'0080 0A88> AD1SAR <When reset: indeterminate> Bit Name Function No functions assigned – 6-15 AD1SAR • A-D successive approximation value (A-D1 successive approximation (A-D conversion mode) value/comparison value) •...
Page 454: A-D Comparate Data Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.8 A-D Comparate Data Registers A-D0 Comparate Data Register (AD0CMP) <Address: H'0080 008C> CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 CMP10 CMP11 CMP12 CMP13 CMP14 CMP15 <When reset: indeterminate> Bit Name Function 0-15 AD0CMP0 AD0CMP15...
Page 455 A-D CONVERTERS 11.2 A-D Converter Related Registers A-D1 Comparate Data Register (AD1CMP) <Address: H'0080 0A8C> CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 CMP10 CMP11 CMP12 CMP13 CMP14 CMP15 <When reset: indeterminate> Bit Name Function 0-15 AD1CMP0 AD1CMP15 0: Analog input voltage >...
Page 456: 10-Bit A-D Data Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.9 10-bit A-D Data Registers 10-bit A-D0 Data Register 0 (AD0DT0) <Address: H'0080 0090> 10-bit A-D0 Data Register 1 (AD0DT1) <Address: H'0080 0092> 10-bit A-D0 Data Register 2 (AD0DT2) <Address: H'0080 0094> 10-bit A-D0 Data Register 3 (AD0DT3) <Address: H'0080 0096>...
Page 457 A-D CONVERTERS 11.2 A-D Converter Related Registers 10-bit A-D1 Data Register 0 (AD1DT0) <Address: H'0080 0A90> 10-bit A-D1 Data Register 1 (AD1DT1) <Address: H'0080 0A92> 10-bit A-D1 Data Register 2 (AD1DT2) <Address: H'0080 0A94> 10-bit A-D1 Data Register 3 (AD1DT3) <Address: H'0080 0A96>...
Page 458: 8-Bit A-D Data Registers
A-D CONVERTERS 11.2 A-D Converter Related Registers 11.2.10 8-bit A-D Data Registers 8-bit A-D0 Data Register 0 (AD08DT0) <Address: H'0080 00D1> 8-bit A-D0 Data Register 1 (AD08DT1) <Address: H'0080 00D3> 8-bit A-D0 Data Register 2 (AD08DT2) <Address: H'0080 00D5> 8-bit A-D0 Data Register 3 (AD08DT3) <Address: H'0080 00D7>...
Page 459 A-D CONVERTERS 11.2 A-D Converter Related Registers 8-bit A-D1 Data Register 0 (AD18DT0) <Address: H'0080 0AD1> 8-bit A-D1 Data Register 1 (AD18DT1) <Address: H'0080 0AD3> 8-bit A-D1 Data Register 2 (AD18DT2) <Address: H'0080 0AD5> 8-bit A-D1 Data Register 3 (AD18DT3) <Address: H'0080 0AD7>...
Page 460: Functional Description Of The A-D Converters
A-D CONVERTERS 11.3 Functional Description of the A-D Converters 11.3 Functional Description of the A-D Converters 11.3.1 How to Find Analog Input Voltages The A-D converters each use a 10-bit successive approximation method. Therefore, to find the actual analog input voltages from the digital quantities obtained as a result of A-D conversion, use the equation below.
Page 461: A-D Conversion Of Successive Approximation Method
A-D CONVERTERS 11.3 Functional Description of the A-D Converters 11.3.2 A-D Conversion of Successive Approximation Method The A-D converter starts A-D convert operation as initiated by a hardware or software A-D conversion start trigger. One A-D conversion starts, the following operations are executed automatically.
Page 462 A-D CONVERTERS 11.3 Functional Description of the A-D Converters The comparison result is stored in the 10-bit A-D Data Registers (AD0DTn or AD1DTn) corresponding to the converted channel. Also, the 8 high-order bits of the A-D conversion result can be obtained by reading the 8-bit A-D Data Registers (AD08DTn or AD18DTn). The following shows how A-D conversion of the successive approximation method is performed in each operation mode.
Page 463: Comparator Operation
A-D CONVERTERS 11.3 Functional Description of the A-D Converters 11.3.3 Comparator Operation When comparator mode (single mode only) is selected, the A-D converter functions as a comparator to compare the comparison voltage set in software and the analog input voltages. Upon writing a comparison value to the Successive Approximation Register, the A-D converter starts "comparating"...
Page 464: Calculating The A-D Conversion Time
A-D CONVERTERS 11.3 Functional Description of the A-D Converters 11.3.4 Calculating the A-D Conversion Time The A-D conversion time is expressed by the sum of a dummy cycle time and the actual execution cycle time. The terms needed for calculation of the conversion time are listed below. (a) Start dummy time The time from when the CPU executes an A-D conversion start instruction to when the A-D Converter starts A-D conversion...
Page 465 A-D CONVERTERS 11.3 Functional Description of the A-D Converters <Single mode> Transfer to A-D A-D conversion Convert operation starts data register start trigger Start dummy Execution cycle End dummy <Scan mode> (Channel 0) (Channel 1) Scan interval Start dummy Execution cycle Execution cycle dummy (Last channel)
Page 466 A-D CONVERTERS 11.3 Functional Description of the A-D Converters Table 11.3.2 A-D Conversion Time when Started by Software Trigger (Total Time) Conversion started by Conversion speed Conversion mode (Note 1) Conversion time [BCLK] Software trigger Low speed mode: Normal Single mode n channels scanned (298 ×...
Page 467 A-D CONVERTERS 11.3 Functional Description of the A-D Converters Table 11.3.3 A-D Conversion Time when Started by Hardware Trigger (Total Time) Conversion started by Conversion speed Conversion mode (Note 1) Conversion time [BCLK] Hardware trigger Low speed mode: Normal Single mode n channels scanned (298 ×...
Page 468: Definition Of The A-D Conversion Accuracy
A-D CONVERTERS 11.3 Functional Description of the A-D Converters 11.3.5 Definition of the A-D Conversion Accuracy The accuracy of the A-D Converter is expressed by absolute accuracy. Absolute accuracy refers to the difference, expressed in terms of LSB, between the output code actually obtained by A-D converting the analog input voltage and the output code that can be expected from an A-D converter with ideal characteristics.
Page 469 A-D CONVERTERS 11.3 Functional Description of the A-D Converters H'00B Ideal A-D conversion characteristic H'00A H'009 H'008 +2 LSB H'007 H'006 A-D conversion characteristic with H'005 infinite resolution H'004 H'003 –2 LSB H'002 H'001 H'000 → Analog input voltage [mV] Figure 11.3.5 Absolute Accuracy of the A-D Converter 11-53 Rev.1.0...
Page 470: Precautions On Using The A-D Converters
A-D CONVERTERS 11.4 Precautions on Using the A-D Converters 11.4 Precautions on Using the A-D Converters • Forcible termination during scan operation If A-D conversion is forcibly stopped during scan mode operation by setting the A-D conversion stop bit (AD0CSTP or AD1CSTP) to 1 and the A-D data register for the channel in the middle of conversion is read, the data obtained by this read is the last conversion result that was transferred to the register before being forcibly stopped.
Page 471: Chapter 12 Serial I/O
CHAPTER 12 CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O 12.2 Serial I/O Related Registers 12.3 Transmit Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.5 Precautions on Using CSIO Mode 12.6 Transmit Operation in UART Mode 12.7 Receive Operation in UART Mode 12.8 Fixed Period Clock Output...
Page 472 12.1 Outline of Serial I/O 12.1 Outline of Serial I/O The 32172/32173 contains a total of eight serial I/O channels, SIO0 through SIO7. Serial channels SIO0, SIO1, SIO4, and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O). SIO2, SIO3, SIO6, and SIO7 are used in UART mode only.
Page 473 SERIAL I/O 12.1 Outline of Serial I/O Table 12.1.1 Outline of Serial I/O Item Content Number of channels CSIO/UART: 4 channels (SIO0,SIO1,SIO4,SIO5) UART-only : 4 channels (SIO2,SIO3,SIO6,SIO7) Clock During CSIO mode : Internal clock or external clock selectable (Note 1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex...
Page 474 SERIAL I/O 12.1 Outline of Serial I/O Table 12.1.2 Interrupt Request Generation Functions of Serial I/O Serial I/O interrupt request Interrupt source on ICU SIO0 transmit buffer empty interrupt SIO0 transmit interrupt SIO0 receive complete or receive error interrupt SIO0 receive interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 transmit interrupt...
Page 475 SERIAL I/O 12.1 Outline of Serial I/O Table 12.1.3 DMA Transfer Request Generation Functions of Serial I/O Serial I/O DMA transfer request DMA input channel SIO0 transmit buffer empty Channel 3 SIO0 receive complete Channel 4 SIO1 transmit buffer empty Channel 6 SIO1 receive complete Channel 3...
Page 476 SERIAL I/O 12.1 Outline of Serial I/O SIO0 SIO0 Transmit Buffer Register Transmit interrupt To Interrupt TXD0 Receive interrupt SIO0 Transmit Shift Register Controller Transmit/ Receive Control Circuit Transmit DMA transfer request To DMA3 SIO0 Receive Shift Register RXD0 Receive DMA transfer request To DMA4 SIO0 Receive Buffer Register UART...
Page 477 SERIAL I/O 12.1 Outline of Serial I/O SIO4 Transmit interrupt TXD4 SIO4 Transmit Shift Register To Interrupt Transmit/ Receive interrupt Controller Receive Transmit DMA transfer request Control Circuit To DMA5 RXD4 Receive DMA transfer request SIO4 Receive Shift Register To DMA1 SCLKI4 SCLKO4 SIO5...
Page 478 SERIAL I/O 12.2 Serial I/O Related Registers 12.2 Serial I/O Related Registers A serial I/O related register map is shown below. Address +0 address +1 address SIO23 Interrupt Status Register SIO03 Interrupt Mask Register H'0080 0100 (SI23STAT) (SI03MASK) SIO03 Receive Interrupt Cause Select Register H'0080 0102 (SI03SEL) SIO0 Transmit Control Register...
Page 479 SERIAL I/O 12.2 Serial I/O Related Registers Address +0 address +1 address SIO4 Transmit/Receive Mode Register SIO4 Transmit Control Register H'0080 0A10 (S4MOD) (S4TCNT) SIO4Transmit Buffer Register H'0080 0A12 (S4TXB) SIO4 Receive Buffer Register H'0080 0A14 (S4RXB) SIO4 Baud Rate Register H'0080 0A16 SIO4 Receive Control Register (S4RCNT)
Page 480: Sio Interrupt Related Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.1 SIO Interrupt Related Registers (1) Selecting interrupt sources The interrupt signals output from each SIO to the ICU (Interrupt Controller) consist of transmit and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty. Receive interrupts can be selected between receive complete and receive error interrupts by using the Receive Interrupt Source Select Register (SI03SEL or SI47SEL).
Page 481 SERIAL I/O 12.2 Serial I/O Related Registers • Receive-complete DMA transfer requests This DMA transfer request is generated when the receive buffer is full. RFIN (Receive complete bit) Receive DMA transfer request Note: If a receive error occurs, no receive-complete DMA transfer requests are generated. Figure 12.2.4 Receive-complete DMA Transfer Request 12-11 Rev.1.0...
Page 482: Sio Interrupt Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.2 SIO Interrupt Control Registers SIO23 Interrupt Status Register (SI23STAT) <Address: H'0080 0100> IRQT2 IRQR2 IRQT3 IRQR3 <When reset: H'00> Bit Name Function No functions assigned – IRQT2 (SIO2 transmit-complete 0: Interrupt not requested interrupt request status bit) 1: Interrupt requested IRQR2 (SIO2 receive interrupt...
Page 483 SERIAL I/O 12.2 Serial I/O Related Registers SIO67 Interrupt Status Register (SI67STAT) <Address: H'0080 0A00> IRQT6 IRQR6 IRQT7 IRQR7 <When reset: H'00> Bit Name Function No functions assigned – IRQT6 (SIO6 transmit-complete 0: Interrupt not requested interrupt request status bit) 1: Interrupt requested IRQR6 (SIO6 receive interrupt 0: Interrupt not requested...
Page 484 SERIAL I/O 12.2 Serial I/O Related Registers SIO03 Interrupt Mask Register (SI03MASK) <Address: H'0080 0101> T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK <When reset: H'00> Bit Name Function T0MASK (SIO0 transmit 0: Masks (disables) interrupt request interrupt mask bit) 1: Enables interrupt request R0MASK (SIO0 receive 0: Masks (disables) interrupt request...
Page 485 SERIAL I/O 12.2 Serial I/O Related Registers SIO47 Interrupt Mask Register (SI47MASK) <Address: H'0080 0A01> T4MASK R4MASK T5MASK R5MASK T6MASK R6MASK T7MASK R7MASK <When reset: H'00> Bit Name Function T4MASK (SIO4 transmit 0: Masks (disables) interrupt request interrupt mask bit) 1: Enables interrupt request R4MASK (SIO4 receive 0: Masks (disables) interrupt request...
Page 486 SERIAL I/O 12.2 Serial I/O Related Registers SIO03 Receive Interrupt Cause Select Register (SI03SEL) <Address: H'0080 0102> ISR0 ISR1 ISR2 ISR3 <When reset: H'00> Bit Name Function No functions assigned – ISR0 0: Receive complete interrupt (SIO0 receive interrupt cause select bit) 1: Receive error interrupt ISR1 0: Receive complete interrupt...
Page 487 SERIAL I/O 12.2 Serial I/O Related Registers SIO47 Receive Interrupt Cause Select Register (SI47SEL) <Address: H'0080 0A02> ISR4 ISR5 ISR6 ISR7 <When reset: H'00> Bit Name Function No functions assigned – ISR4 0: Receive complete interrupt (SIO4 receive interrupt cause select bit) 1: Receive error interrupt ISR5 0: Receive complete interrupt...
Page 488 SERIAL I/O 12.2 Serial I/O Related Registers <SI23STAT: H'0080 0100> <SI03MASK: H'0080 0101> TXD2 Data bus 4-source inputs IRQT2 SIO2,3 transmit/receive T2MASK (Level) interrupt RXD2 receive complete RXD2 receive error IRQR2 ISR2 R2MASK TXD3 IRQT3 T3MASK RXD3 receive complete RXD3 receive error IRQR3 ISR3 R3MASK...
Page 489: Sio Transmit Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.3 SIO Transmit Control Registers SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140>...
Page 490 SERIAL I/O 12.2 Serial I/O Related Registers (1) CDIV (baud rate generator count source select) bits (D2, D3) These bits select the count source for the Baud Rate Generator (BRG). Note: If f(BCLK) is selected for the BRG count source, the BRG must be set in such a way that the baud rate will not exceed the maximum transfer rate.
Page 491: Sio Transmit/Receive Mode Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.4 SIO Transmit/Receive Mode Registers SIO0 Transmit/Receive Mode Registers (S0MOD) <Address: H'0080 0111> SIO1 Transmit/Receive Mode Registers (S1MOD) <Address: H'0080 0121> SIO2 Transmit/Receive Mode Registers (S2MOD) <Address: H'0080 0131> SIO3 Transmit/Receive Mode Registers (S3MOD) <Address: H'0080 0141>...
Page 492 SERIAL I/O 12.2 Serial I/O Related Registers The SIO Transmit/Receive Mode Registers consist of the bits to select serial I/O operation mode, data format, and the function to be used during communication. The SIO Transmit/Receive Mode Registers must always be set before serial I/O starts operation. To modify the register contents after the SIO started sending or receiving, check to see that the transmit or receive operation is completed and disable transmit/receive operations (by clearing the SIO Transmit Control Register transmit enable bit and the SIO Receive Control Register receive...
Page 493 SERIAL I/O 12.2 Serial I/O Related Registers ST:Start Bit PAR: Parity Bit :Equivalent to one frame D: Data Bit SP: Stop Bit Direction of transfer • Clock synchronized mode Note 1 Note 2 • 7-bit UART mode Note 1 Note 2 •...
Page 494: Sio Transmit Buffer Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.5 SIO Transmit Buffer Registers SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142>...
Page 495: Sio Receive Buffer Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.6 SIO Receive Buffer Registers SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144>...
Page 496: Sio Receive Control Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.7 SIO Receive Control Registers SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146>...
Page 497 SERIAL I/O 12.2 Serial I/O Related Registers (1) RSTAT (Receive status) bit (D1) [Set condition] This bit is set to 1 by starting receive operation. When this bit is 1, it means that the SIO is receiving data. [Clear condition] This bit is cleared upon completion of receive operation or by clearing the REN (receive enable) bit to 0.
Page 498 SERIAL I/O 12.2 Serial I/O Related Registers (5) PTY (Parity error) bit (D5) This bit is effective in only UART mode. It is fixed to 0 during CSIO mode. [Set condition] This bit is set to 1 when while the SIO Transmit/Receive Mode Register PEN (parity enable/disable) bit is enabled, the parity (even/odd) of the received data does not match the one selected with the said register's PSEL (parity select) bit.
Page 499: Sio Baud Rate Registers
SERIAL I/O 12.2 Serial I/O Related Registers 12.2.8 SIO Baud Rate Registers SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147>...
Page 500 SERIAL I/O 12.2 Serial I/O Related Registers frequency is divided by (n + 1) where n = BRG set value and is further divided by 16 to produce the transmit/receive shift clock. When using SIO0, SIO1, SIO4, or SIO5 in UART mode, the SIO's corresponding port (P84, P87, P65, or P66) may be changed to the SCLKO pin, so that a divided-by-2 clock of BRG output is generated.
Page 501: Transmit Operation In Csio Mode
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3 Transmit Operation in CSIO Mode 12.3.1 Setting the CSIO Baud Rate The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which to generate the transmit/receive shift clock is selected from the internal clock f(BCLK) or external clock.
Page 502: Initial Settings For Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.2 Initial Settings for CSIO Transmission To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to CSIO mode •...
Page 503 SERIAL I/O 12.3 Transmit Operation in CSIO Mode Initial settings for CSIO transmission • Set register to CSIO mode Set SIO Transmit/Receive Mode Register • Select internal or external clock Set SIO Transmit Control Register • Select clock divider's divide-by ratio (Note 1) Serial I/O related...
Page 504: Starting Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.3 Starting CSIO Transmission When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. (1) Transmit conditions when CSIO mode internal clock is selected •...
Page 505: Processing At End Of Csio Transmission
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.5 Processing at End of CSIO Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively •...
Page 506 SERIAL I/O 12.3 Transmit Operation in CSIO Mode The following processing is automatically executed in hardware CSIO transmit operation starts Transmit conditions met? (Note) Transmit interrupt request • Transfer content of transmit buffer to transmit shift register Transmit DMA • Set transmit buffer empty bit to 1 transfer request Transmit data Transmit...
Page 507: Typical Csio Transmit Operation
SERIAL I/O 12.3 Transmit Operation in CSIO Mode 12.3.8 Typical CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode. <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI Internal clock selected External clock selected <CSIO on transmit side> Transmit clock (SCLKO) Transmit enable bit...
Page 508 SERIAL I/O 12.3 Transmit Operation in CSIO Mode <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI Internal clock selected External clock selected <CSIO on transmit side> Transmit clock (SCLKO) Transmit enable bit Write to Write to Cleared transmit transmit buffer buffer...
Page 509: Receive Operation In Csio Mode
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.4.1 Initial Settings for CSIO Reception To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation even when you only want to receive data.
Page 510 SERIAL I/O 12.4 Receive Operation in CSIO Mode (8) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") Initial settings for CSIO reception •...
Page 511: Starting Csio Reception
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.2 Starting CSIO Reception When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. (1) Receive conditions when CSIO mode internal clock is selected •...
Page 512: About Successive Reception
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.4 About Successive Reception When the following conditions are met at completion of data reception, data may be received successively. • The receive enable bit is set to 1. • Transmit conditions are met. •...
Page 513: Flags Indicating The Status Of Csio Receive Operation
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.5 Flags Indicating the Status of CSIO Receive Operation Following flags are available that indicate the status of receive operation in CSIO mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit •...
Page 514: Typical Csio Receive Operation
SERIAL I/O 12.4 Receive Operation in CSIO Mode 12.4.6 Typical CSIO Receive Operation The following shows a typical receive operation in CSIO mode. <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI Internal clock selected External clock selected <CSIO on receive side> Receive clock Clock stopped (SCLKI)
Page 515 SERIAL I/O 12.4 Receive Operation in CSIO Mode <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI Internal clock selected External clock selected <CSIO on receive side> Transmit clock (SCLKO) Cleared First data reception Next data reception Receive enable bit completed completed Receive buffer not read...
Page 516: Precautions On Using Csio Mode
SERIAL I/O 12.5 Precautions on Using CSIO Mode 12.5 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating.
Page 517 SERIAL I/O 12.5 Precautions on Using CSIO Mode • About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data.
Page 518: Transmit Operation In Uart Mode
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6 Transmit Operation in UART Mode 12.6.1 Setting the UART Baud Rate The baud rate (data transfer rate) during UART mode is determined by a transmit/receive shift clock. In UART mode, the source for this transmit/receive shift clock is always the internal clock regardless of how the internal/external clock select bit (SIO Transmit/Receive Mode Register bit D11) is set.
Page 519: Uart Transmit/Receive Data Formats
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.2 UART Transmit/Receive Data Formats The transmit/receive data format during UART mode is determined by setting the SIO Transmit/ Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode.
Page 520 SERIAL I/O 12.6 Transmit Operation in UART Mode 7-bit characters 8-bit characters 9-bit characters ST : Start bit D0 - D7 : Character (data) bits PAR : Parity bit SIO Transmit Buffer Register SP : Stop bit SIO Receive Buffer Register D7 D8 7-bit characters 8-bit characters...
Page 521: Initial Settings For Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.3 Initial Settings for UART Transmission To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to UART mode •...
Page 522 SERIAL I/O 12.6 Transmit Operation in UART Mode Initial settings for UART transmission • Set register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set stop bit length • Set character length •...
Page 523: Starting Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.4 Starting UART Transmission When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. • The SIO Transmit Control Register's TEN (transmit enable) bit is set to 1. (Note) •...
Page 524: Processing At End Of Uart Transmission
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.6 Processing at End of UART Transmission When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is set to 0. (2) When transmitting successively •...
Page 525 SERIAL I/O 12.6 Transmit Operation in UART Mode The following processing is automatically executed in hardware UART transmit operation starts Transmit conditions met? (Note) Transmit interrupt request • Transfer content of transmit buffer to transmit shift register Transmit DMA • Set transmit buffer empty bit to 1 transfer request Transmit data Transmit...
Page 526: Typical Uart Transmit Operation
SERIAL I/O 12.6 Transmit Operation in UART Mode 12.6.9 Typical UART Transmit Operation The following shows a typical transmit operation in CSIO mode. <UART on transmit side> <UART on receive side> <UART on transmit side> Transmit enable bit Write to transmit Cleared buffer register...
Page 527 SERIAL I/O 12.6 Transmit Operation in UART Mode <UART on transmit side> <UART on receive side> <UART on transmit side> Transmit enable bit Write to Write to Cleared transmit transmit buffer buffer register register (First data) (Next data) Transmit buffer empty bit Cleared when transmission Transferred from...
Page 528: Receive Operation In Uart Mode
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7 Receive Operation in UART Mode 12.7.1 Initial Settings for UART Reception To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register •...
Page 529 SERIAL I/O 12.7 Receive Operation in UART Mode Initial settings for UART reception • Set register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set stop bit length • Set character length Set SIO Transmit Control Register •...
Page 530: Starting Uart Reception
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.2 Starting UART Reception When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. • The SIO Receive Control Register's receive enable bit is set to 1 •...
Page 531 SERIAL I/O 12.7 Receive Operation in UART Mode The following processing is automatically executed in hardware UART receive operation starts Transmit conditions met? Start bit detected normally? Set receive status bit to 1 Receive data Overrun error? Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register's overrun error bit...
Page 532: Typical Uart Receive Operation
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.4 Typical UART Receive Operation The following shows a typical receive operation in UART mode. <UART on receive side> <UART on transmit side> Internal clock selected <UART on receive side> Receive enable bit (SIO Receive Control Register) Cleared...
Page 533 SERIAL I/O 12.7 Receive Operation in UART Mode <UART on receive side> <UART on transmit side> <UART on receive side> Receive enable bit First data reception Next data reception (SIO Receive completed completed Control Register) Receive buffer not read during this interval Receive-finished bit (Note 5) Overrun error bit...
Page 534: Fixed Period Clock Output Function
SERIAL I/O 12.8 Fixed Period Clock Output Function 12.8 Fixed Period Clock Output Function When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84, P87, P65 or P66) to function as the SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin. In this way, a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin.
Page 535: Precautions On Using Uart Mode
SERIAL I/O 12.9 Precautions on Using UART Mode 12.9 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating.
Page 536 SERIAL I/O 12.9 Precautions on Using UART Mode • Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode. • SIO Receive Control Register receive status bit • SIO Receive Control Register receive-finished bit •...
Page 537: Chapter 13 Can Modules
CHAPTER 13 CHAPTER 13 CAN MODULES 13.1 Outline of the CAN Modules 13.2 CAN Module Related Registers 13.3 CAN Protocol 13.4 Initialization of the CAN Module 13.5 Transmitting Data Frames 13.6 Receiving Data Frames 13.7 Transmitting Remote Frames 13.8 Receiving Remove Frames...
Page 538 13.1 Outline of the CAN Modules 13.1 Outline of the CAN Modules The 32172/32173 contains two Full CAN modules (CAN0 and CAN1) compliant with CAN (Controller Area Network) Specification 2.0B active. CAN0 and CAN1 each have 16 message slots and three mask registers. Making use of these message slots and mask registers helps to reduce data processing load on the CPU.
Page 539 ADDRESS SPACE 13.1 Outline of the Address Space Table 13.1.2 Interrupt Generating Functions of the CAN Modules CAN module interrupt source ICU interrupt source CAN0 transmit complete interrupt CAN0 transmit/receive & error interrupt CAN0 receive complete interrupt CAN0 transmit/receive & error interrupt CAN0 bus error interrupt CAN0 transmit/receive &...
Page 540 CAN MODULES 13.1 Outline of the CAN Modules Data bus CAN0 Global Mask CAN0 Status Message Memory CAN0 Message Slot Register Register 0-15 Control Register CAN0 REC CAN0 Local Mask (1) Message ID CAN0 Extended Register A Register (2) Data length code ID Register CAN0 Local Mask CAN0 TEC...
Page 541 CAN MODULES 13.2 CAN Module Related Registers 13.2 CAN Module Related Registers A CAN module related register map is shown below. Address +0 address +1 address D7 D8 H'0080 1000 CAN0 Control Register(CAN0CNT) H'0080 1002 CAN0 Status Register(CAN0STAT) H'0080 1004 CAN0 Extended ID Register(CAN0EXTID) H'0080 1006 CAN0 Configuration Register(CAN0CONF)
Page 542 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN0 Message Slot 0 Standard ID0(C0MSL0SID0) CAN0 Message Slot 0 Standard ID1(C0MSL0SID1) H'0080 1100 CAN0 Message Slot 0 Extended ID0(C0MSL0EID0) CAN0 Message Slot 0 Extended ID1(C0MSL0EID1) H'0080 1102 CAN0 Message Slot 0 Extended ID2(C0MSL0EID2) CAN0 Message Slot 0 Data Length Register(C0MSL0DLC)
Page 543 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN0 Message Slot 5 Extended ID2(C0MSL5EID2) CAN0 Message Slot 5 Data Length Register(C0MSL5DLC) H'0080 1154 CAN0 Message Slot 5 Data 0(C0MSL5DT0) H'0080 1156 CAN0 Message Slot 5 Data 1(C0MSL5DT1) H'0080 1158 CAN0 Message Slot 5 Data 2(C0MSL5DT2) CAN0 Message Slot 5 Data 3(C0MSL5DT3)
Page 544 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN0 Message Slot 10 Data 2(C0MSL10DT2) CAN0 Message Slot 10 Data 3(C0MSL10DT3) H'0080 11A8 H'0080 11AA CAN0 Message Slot 10 Data 4(C0MSL10DT4) CAN0 Message Slot 10 Data 5(C0MSL10DT5) H'0080 11AC CAN0 Message Slot 10 Data 6(C0MSL10DT6) CAN0 Message Slot 10 Data 7(C0MSL10DT7)
Page 545 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 H'0080 1400 CAN1 Control Register(CAN1CNT) H'0080 1402 CAN1 Status Register(CAN1STAT) H'0080 1404 CAN1 Extended ID Register(CAN1EXTID) H'0080 1406 CAN1 Configuration Register(CAN1CONF) H'0080 1408 CAN1 Time stamp Count Register(CAN1TSTMP) CAN1 Transmit Error Count Register(CAN1TEC) H'0080 140A CAN1 Receive Error Count Register(CAN1REC)
Page 546 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN1 Message Slot 0 Standard ID0(C1MSL0SID0) CAN1 Message Slot 0 Standard ID1(C1MSL0SID1) H'0080 1500 CAN1 Message Slot 0 Extended ID0(C1MSL0EID0) CAN1 Message Slot 0 Extended ID1(C1MSL0EID1) H'0080 1502 CAN1 Message Slot 0 Data Length Register(C1MSL0DLC) H'0080 1504...
Page 547 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN1 Message Slot 5 Extended ID2(C1MSL5EID2) CAN1 Message Slot 5 Data Length Register(C1MSL5DLC) H'0080 1554 CAN1 Message Slot 5 Data 0(C1MSL5DT0) H'0080 1556 CAN1 Message Slot 5 Data 1(C1MSL5DT1) H'0080 1558 CAN1 Message Slot 5 Data 2(C1MSL5DT2) CAN1 Message Slot 5 Data 3(C1MSL5DT3)
Page 548 CAN MODULES 13.2 CAN Module Related Registers Address +0 address +1 address D7 D8 CAN1 Message Slot 10 Data 2(C1MSL10DT2) CAN1 Message Slot 10 Data 3(C1MSL10DT3) H'0080 15A8 H'0080 15AA CAN1 Message Slot 10 Data 4(C1MSL10DT4) CAN1 Message Slot 10 Data 5(C1MSL10DT5) H'0080 15AC CAN1 Message Slot 10 Data 7(C1MSL10DT7) CAN1 Message Slot 10 Data 6(C1MSL10DT6)
Page 549: Can Control Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.1 CAN Control Registers CAN0 Control Register (CAN0CNT) <Address: H'0080 1000> CAN1 Control Register (CAN1CNT) <Address: H'0080 1400> RBO TSR FRST BCM LBM RST <When reset: H'0011> Bit Name Function No functions assigned –...
Page 550 CAN MODULES 13.2 CAN Module Related Registers (1) RBO (Return bus off) bit (D4) The receive error counter (CANREC)/transmit error counter (CANTEC) can be cleared by setting this bit to 1, thereby placing the CAN module forcibly in an error active state. This bit is automatically cleared when an error active state is entered.
Page 551 CAN MODULES 13.2 CAN Module Related Registers (5) BCM (BasicCAN mode) bit (D12) The CAN module can be run in BasicCA N mode by setting this bit to 1. • Operation during BasicCAN mode In BasicCAN mode, two local slots-slots 14 and 15 -are used as double buffers, and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15.
Page 552 CAN MODULES 13.2 CAN Module Related Registers (7) RST (CAN reset) bit (D15) When the RST bit is cleared to 0, the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits. Also, the CAN Time stamp Count Register thereby starts counting.
Page 553: Can Status Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.2 CAN Status Registers CAN0 Status Register (CAN0STAT) <Address: H'0080 1002> CAN1 Status Register (CAN1STAT) <Address: H'0080 1402> BOS EPS CBS BCS LBS CRS RSB TSB RSC TSC <When reset: H'0100> Bit Name Function No functions assigned –...
Page 554 CAN MODULES 13.2 CAN Module Related Registers Bit Name Function 12-15 Message slot number which has had (Message slot number) transmission/reception completed – 0000: Slot 0 0001: Slot 1 0010: Slot 2 0011: Slot 3 0100: Slot 4 0101: Slot 5 0110: Slot 6 0111: Slot 7 1000: Slot 8...
Page 555 CAN MODULES 13.2 CAN Module Related Registers (3) CBS (CAN bus error) bit (D3) [Set condition] This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when the CAN module finished transmitting or receiving normally. (4) BCS (BasicCAN status) bit (D4) When the BCS bit = 1, it means that the CAN module is operating in BasicCAN mode.
Page 556 CAN MODULES 13.2 CAN Module Related Registers (7) RSB (Receive status) bit (D8) [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module starts operating as a transmit node or goes to a bus-idle state.
Page 557: Can Extended Id Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.3 CAN Extended ID Registers CAN0 Extended ID Register (CAN0EXTID) <Address: H'0080 1004> CAN1 Extended ID Register (CAN1EXTID) <Address: H'0080 1404> IDE0 IDE1 IDE2 IDE3 IDE4 IDE5 IDE6 IDE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15 <When reset: H'0000>...
Page 558: Can Configuration Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.4 CAN Configuration Registers CAN0 Configuration Register (CAN0CONF) <Address: H'0080 1006> CAN1 Configuration Register (CAN1CONF) <Address: H'0080 1406> <When reset: H'0000> Bit Name Function Sets reSynchronization Jump Width (reSynchronization Jump Width) 00 : SJW = 1Tq 01 : SJW = 2Tq 10 : SJW = 3Tq 11 : SJW = 4Tq...
Page 559 CAN MODULES 13.2 CAN Module Related Registers <When reset: H'0000> Bit Name Function Sets Phase Segment1 (Phase Segment1) 000 : Phase Segment1 = 1Tq 001 : Phase Segment1 = 2Tq 010 : Phase Segment1 = 3Tq 011 : Phase Segment1 = 4Tq 100 : Phase Segment1 = 5Tq 101 : Phase Segment1 = 6Tq 110 : Phase Segment1 = 7Tq...
Page 560 CAN MODULES 13.2 CAN Module Related Registers (5) SAM bit (D11) This bit sets the number of times each bit is sampled. When SAM = 0, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit.
Page 561: Can Time Stamp Count Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.5 CAN Time stamp Count Registers CAN0 Time stamp Count Register (CAN0TSTMP) <Address: H'0080 1008> CAN1 Time stamp Count Register (CAN1TSTMP) <Address: H'0080 1408> CANTSTMP <When reset: H'0000> Bit Name Function 0-15 CANiTSTMP 16-bit counter value –...
Page 562: Can Error Count Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.6 CAN Error Count Registers CAN0 Receive Error Count Register (CAN0REC) <Address: H'0080 100A> CAN1 Receive Error Count Register (CAN1REC) <Address: H'0080 140A> <When reset: H'00> Bit Name Function Receive error count value –...
Page 563: Can Baud Rate Prescalers
CAN MODULES 13.2 CAN Module Related Registers 13.2.7 CAN Baud Rate Prescalers CAN0 Baud Rate Prescaler (CAN0BRP) <Address: H'0080 1016> CAN1 Baud Rate Prescaler (CAN1BRP) <Address: H'0080 1416> CANBRP <When reset: H'01> Bit Name Function Selects a baud rate prescaler value This register is used to set the CAN module Tq period.
Page 564: Can Interrupt Related Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.8 CAN Interrupt Related Registers CAN0 Slot Interrupt Status Register (CAN0SLIST) <Address: H'0080 100C> CAN1 Slot Interrupt Status Register (CAN1SLIST) <Address: H'0080 140C> SSB0 SSB1 SSB2 SSb3 SSB4 SSB5 SSB6 SSB7 SSB8 SSB9 SSB10 SSB11 SSB12 SSB13SSB14 SSB15 <When reset: H'0000>...
Page 565 CAN MODULES 13.2 CAN Module Related Registers When using CAN interrupts, it is possible to know which slot has requested an interrupt by inspecting this register. • Slots set for transmission The status bit is set to 1 when transmission is completed. This bit is cleared by writing 0 in software.
Page 566 CAN MODULES 13.2 CAN Module Related Registers CAN0 Slot Interrupt Mask Register (CAN0SLIMK) <Address: H'0080 1010> CAN1 Slot Interrupt Mask Register (CAN1SLIMK) <Address: H'0080 1410> IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15 <When reset: H'0000>...
Page 567 CAN MODULES 13.2 CAN Module Related Registers CAN0 Error Interrupt Status Register (CAN0ERIST) <Address: H'0080 1014> CAN1 Error Interrupt Status Register (CAN1ERIST) <Address: H'0080 1414> <When reset: H'00> Bit Name Function No functions assigned – 0: Interrupt not requested (CAN bus error interrupt status) 1: Interrupt requested (Error passive interrupt status) (Bus off interrupt status)
Page 568 CAN MODULES 13.2 CAN Module Related Registers CAN0 Error Interrupt Mask Register (CAN0ERIMK) <Address: H'0080 1015> CAN1 Error Interrupt Mask Register (CAN1ERIMK) <Address: H'0080 1415> <When reset: H'00> Bit Name Function 8-12 No functions assigned – 0: Masks (disables) interrupt request (CAN bus error interrupt mask) 1: Enables interrupt request PIMm...
Page 569 CAN MODULES 13.2 CAN Module Related Registers CAN0SLIST <H'0080 100C> CAN0SLIMK <H'0080 1010> Slot 0 transmit/receive complete Data bus 19-source inputs SSB0 CAN0 transmit/receive IRB0 (Level) & error interrupt Slot 1 transmit/receive complete SSB1 IRB1 Slot 2 transmit/receive complete SSB2 IRB2 Slot 3 transmit/receive complete SSB3...
Page 570 CAN MODULES 13.2 CAN Module Related Registers CAN0SLIST <H'0080 100C> CAN0SLIMK <H'0080 1010> Slot 8 transmit/receive complete Data bus 19-source inputs SSB8 To the preceding page IRB8 (Level) Slot 9 transmit/receive complete SSB9 IRB9 Slot 10 transmit/receive complete SSB10 IRB10 Slot 11 transmit/receive complete SSB11 IRB11...
Page 571 CAN MODULES 13.2 CAN Module Related Registers CAN0ERIST <H'0080 1014> CAN0ERIMK <H'0080 1015> CAN bus error occurs Data bus 19-source inputs To the preceding page (Level) Goes to error-passive state Goes to bus-off state Figure 13.2.11 Block Diagram of CAN0 Transmit/Receive & Error Interrupts (3/3) 13-35 Rev.1.0...
Page 572 CAN MODULES 13.2 CAN Module Related Registers CAN1SLIST <H'0080 140C> CAN1SLIMK <H'0080 1410> Slot 0 transmit/receive complete Data bus 19-source inputs SSB0 CAN1 transmit/receive IRB0 (Level) & error interrupt Slot 1 transmit/receive complete SSB1 IRB1 Slot 2 transmit/receive complete SSB2 IRB2 Slot 3 transmit/receive complete SSB3...
Page 573 CAN MODULES 13.2 CAN Module Related Registers CAN1SLIST <H'0080 140C> CAN1SLIMK <H'0080 1410> Slot 8 transmit/receive complete Data bus 19-source inputs SSB8 To the preceding page IRB8 (Level) Slot 9 transmit/receive complete SSB9 IRB9 Slot 10 transmit/receive complete SSB10 IRB10 Slot 11 transmit/receive complete SSB11 IRB11...
Page 574 CAN MODULES 13.2 CAN Module Related Registers CAN1ERIST <H'0080 1414> CAN1ERIMK <H'0080 1415> CAN bus error occurs Data bus 19-source inputs To the preceding page (Level) Goes to error-passive state Goes to bus-off state Figure 13.2.14 Block Diagram of CAN1 Transmit/Receive & Error Interrupts (3/3) 13-38 Rev.1.0...
Page 575: Can Mask Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.9 CAN Mask Registers CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address: H'0080 1028> CAN0 Local Register A Standard ID0 (C0LMSKAS0) <Address: H'0080 1030> CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) <Address: H'0080 1038> CAN1 Global Mask Register Standard ID0 (C1GMSKS0) <Address: H'0080 1428>...
Page 576 CAN MODULES 13.2 CAN Module Related Registers Three mask registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while the Local Mask Registers A and B respectively are used for slots 14 and 15.
Page 577 CAN MODULES 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address: H'0080 102A> CAN0 Local Register A Extended ID0 (C0LMSKAE0) <Address: H'0080 1032> CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) <Address: H'0080 103A> CAN1 Global Mask Register Extended ID0 (C1GMSKE0) <Address: H'0080 142A>...
Page 578 CAN MODULES 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address: H'0080 102C> CAN0 Local Register A Extended ID2 (C0LMSKAE2) <Address: H'0080 1034> CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) <Address: H'0080 103C> CAN1 Global Mask Register Extended ID2 (C1GMSKE2) <Address: H'0080 142C>...
Page 579: Can Message Slot Control Registers
CAN MODULES 13.2 CAN Module Related Registers 13.2.10 CAN Message Slot Control Registers CAN0 Message Slot 0 Control Register (C0MSL0CNT) <Address: H'0080 1050> CAN0 Message Slot 1 Control Register (C0MSL1CNT) <Address: H'0080 1051> CAN0 Message Slot 2 Control Register (C0MSL2CNT) <Address: H'0080 1052>...
Page 580 CAN MODULES 13.2 CAN Module Related Registers D0 (D8) D7 (D15) TRSTAT TRFIN <When reset: H'00> Bit Name Function 0: Does not use the message slot as a transmit (Transmit request) slot 1: Uses the message slot as a transmit slot 0: Does not use the message slot as a receive (Receive request) slot...
Page 581 CAN MODULES 13.2 CAN Module Related Registers (1) TR (Transmit request) bit (D0) Set this bit to 1 when using the message slot as a transmit slot. Set this bit to 0 when using the message slot as a data frame or remote frame receive slot. (2) RR (Receive request) bit (D1) Set this bit to 1 when using the message slot as a receive slot.
Page 582 CAN MODULES 13.2 CAN Module Related Registers (5) RA (Remote active) bit (D4) This bit functions differently between slots 0-13 and slots 14 and 15. • Slots 0-13 For slots which have been set for remote frame transmission (reception), this bit is set to 1. Then when remote frame transmission (or reception) is completed, the bit is cleared to 0.
Page 583 CAN MODULES 13.2 CAN Module Related Registers (8) TRFIN (Transmit/receive finished) bit (D7) This bit indicates that the CAN module has finished transmitting or receiving data. • For transmit slots This bit is set to 1 when the CAN module finishes sending data from the message slot. This bit is cleared by writing 0 in software.
Page 584: Can Message Slots
CAN MODULES 13.2 CAN Module Related Registers 13.2.11 CAN Message Slots CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) <Address: H'0080 1100> CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) <Address: H'0080 1110> CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) <Address: H'0080 1120> CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) <Address: H'0080 1130>...
Page 585 CAN MODULES 13.2 CAN Module Related Registers SID0 SID1 SID2 SID3 SID4 <When reset: indeterminate> Bit Name Function No functions assigned – SID0-SID4 Standard ID0 to standard ID4 (Standard ID0 to standard ID4) These registers comprise a transmit frame/receive frame memory space. 13-49 Rev.1.0...
Page 586 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) <Address: H'0080 1101> CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) <Address: H'0080 1111> CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) <Address: H'0080 1121> CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) <Address: H'0080 1131>...
Page 587 CAN MODULES 13.2 CAN Module Related Registers SID5 SID6 SID7 SID8 SID9 SID10 <When reset: indeterminate> Bit Name Function No functions assigned – 10-15 SID5-SID10 Standard ID5 to standard ID10 (Standard ID5 to standard ID10) These registers comprise a transmit frame/receive frame memory space. 13-51 Rev.1.0...
Page 588 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) <Address: H'0080 1102> CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) <Address: H'0080 1112> CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) <Address: H'0080 1122> CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) <Address: H'0080 1132>...
Page 589 CAN MODULES 13.2 CAN Module Related Registers EID0 EID1 EID2 EID3 <When reset: indeterminate> Bit Name Function No functions assigned – EID0-EID3 Extended ID0 to extended ID3 (Extended ID0 to extended ID3) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate.
Page 590 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) <Address: H'0080 1103> CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) <Address: H'0080 1113> CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) <Address: H'0080 1123> CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) <Address: H'0080 1133>...
Page 591 CAN MODULES 13.2 CAN Module Related Registers EID4 EID5 EID6 EID7 EID8 EID9 EID10 EID11 <When reset: indeterminate> Bit Name Function 8-15 EID4-EID11 Extended ID4 to extended ID11 (Extended ID4 to extended ID11) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate.
Page 592 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) <Address: H'0080 1104> CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) <Address: H'0080 1114> CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) <Address: H'0080 1124> CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) <Address: H'0080 1134>...
Page 593 CAN MODULES 13.2 CAN Module Related Registers EID12 EID13 EID14 EID15 EID16 EID17 <When reset: indeterminate> Bit Name Function No functions assigned – EID12-EID17 Extended ID12 to extended ID17 (Extended ID12 to extended ID17) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate.
Page 594 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) <Address: H'0080 1105> CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) <Address: H'0080 1115> CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) <Address: H'0080 1125> CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) <Address: H'0080 1135>...
Page 595 CAN MODULES 13.2 CAN Module Related Registers DLC0 DLC1 DLC2 DLC3 <When reset: indeterminate> Bit Name Function 8-11 No functions assigned – 12-15 DLC0-DLC3 0 0 0 0 : 0 byte (Set data length) 0 0 0 1 : 1 byte 0 0 1 0 : 2 byte 0 0 1 1 : 3 byte 0 1 0 0 : 4 byte...
Page 596 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 0 (C0MSL0DT0) <Address: H'0080 1106> CAN0 Message Slot 1 Data 0 (C0MSL1DT0) <Address: H'0080 1116> CAN0 Message Slot 2 Data 0 (C0MSL2DT0) <Address: H'0080 1126> CAN0 Message Slot 3 Data 0 (C0MSL3DT0) <Address: H'0080 1136>...
Page 597 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT0 <When reset: indeterminate> Bit Name Function CMSLnDT0 Message slot n data 0 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note 1: For receive slots, if the data length (DLC value) = 0 when storing a data frame, an indeterminate value is written to the register.
Page 598 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 1 (C0MSL0DT1) <Address: H'0080 1107> CAN0 Message Slot 1 Data 1 (C0MSL1DT1) <Address: H'0080 1117> CAN0 Message Slot 2 Data 1 (C0MSL2DT1) <Address: H'0080 1127> CAN0 Message Slot 3 Data 1 (C0MSL3DT1) <Address: H'0080 1137>...
Page 599 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT1 <When reset: indeterminate> Bit Name Function 8-15 CMSLnDT1 Message slot n data 1 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 1 or less when storing a data frame, an indeterminate value is written to the register.
Page 600 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 2 (C0MSL0DT2) <Address: H'0080 1108> CAN0 Message Slot 1 Data 2 (C0MSL1DT2) <Address: H'0080 1118> CAN0 Message Slot 2 Data 2 (C0MSL2DT2) <Address: H'0080 1128> CAN0 Message Slot 3 Data 2 (C0MSL3DT2) <Address: H'0080 1138>...
Page 601 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT2 <When reset: indeterminate> Bit Name Function CMSLnDT2 Message slot n data 2 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 2 or less when storing a data frame, an indeterminate value is written to the register.
Page 602 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 3 (C0MSL0DT3) <Address: H'0080 1109> CAN0 Message Slot 1 Data 3 (C0MSL1DT3) <Address: H'0080 1119> CAN0 Message Slot 2 Data 3 (C0MSL2DT3) <Address: H'0080 1129> CAN0 Message Slot 3 Data 3 (C0MSL3DT3) <Address: H'0080 1139>...
Page 603 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT3 <When reset: indeterminate> Bit Name Function 8-15 CMSLnDT3 Message slot n data 3 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 3 or less when storing a data frame, an indeterminate value is written to the register.
Page 604 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 4 (C0MSL0DT4) <Address: H'0080 110A> CAN0 Message Slot 1 Data 4 (C0MSL1DT4) <Address: H'0080 111A> CAN0 Message Slot 2 Data 4 (C0MSL2DT4) <Address: H'0080 112A> CAN0 Message Slot 3 Data 4 (C0MSL3DT4) <Address: H'0080 113A>...
Page 605 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT4 <When reset: indeterminate> Bit Name Function CMSLnDT4 Message slot n data 4 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 4 or less when storing a data frame, an indeterminate value is written to the register.
Page 606 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 5 (C0MSL0DT5) <Address: H'0080 110B> CAN0 Message Slot 1 Data 5 (C0MSL1DT5) <Address: H'0080 111B> CAN0 Message Slot 2 Data 5 (C0MSL2DT5) <Address: H'0080 112B> CAN0 Message Slot 3 Data 5 (C0MSL3DT5) <Address: H'0080 113B>...
Page 607 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT5 <When reset: indeterminate> Bit Name Function 8-15 CMSLnDT5 Message slot n data 5 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 5 or less when storing a data frame, an indeterminate value is written to the register.
Page 608 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 6 (C0MSL0DT6) <Address: H'0080 110C> CAN0 Message Slot 1 Data 6 (C0MSL1DT6) <Address: H'0080 111C> CAN0 Message Slot 2 Data 6 (C0MSL2DT6) <Address: H'0080 112C> CAN0 Message Slot 3 Data 6 (C0MSL3DT6) <Address: H'0080 113C>...
Page 609 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT6 <When reset: indeterminate> Bit Name Function CMSLnDT6 Message slot n data 6 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 6 or less when storing a data frame, an indeterminate value is written to the register.
Page 610 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 7 (C0MSL0DT7) <Address: H'0080 110D> CAN0 Message Slot 1 Data 7 (C0MSL1DT7) <Address: H'0080 111D> CAN0 Message Slot 2 Data 7 (C0MSL2DT7) <Address: H'0080 112D> CAN0 Message Slot 3 Data 7 (C0MSL3DT7) <Address: H'0080 113D>...
Page 611 CAN MODULES 13.2 CAN Module Related Registers CMSLnDT7 <When reset: indeterminate> Bit Name Function CMSLnDT7 Message slot n data 7 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 7 or less when storing a data frame, an indeterminate value is written to the register.
Page 612 CAN MODULES 13.2 CAN Module Related Registers CAN0 Message Slot 0 Time stamp (C0MSL0TSP) <Address: H'0080 110E> CAN0 Message Slot 1 Time stamp (C0MSL1TSP) <Address: H'0080 111E> CAN0 Message Slot 2 Time stamp (C0MSL2TSP) <Address: H'0080 112E> CAN0 Message Slot 3 Time stamp (C0MSL3TSP) <Address: H'0080 113E>...
Page 613 CAN MODULES 13.2 CAN Module Related Registers CMSLnTSP <When reset: indeterminate> Bit Name Function 0-15 CMSLnTSP Message slot n time stamp n = 0-15 These registers comprise a transmit frame/receive frame memory space. When transmission/ reception is completed, the value of the CAN Time stamp Count Register is stored in this register. 13-77 Rev.1.0...
Page 614: Can Protocol
CAN MODULES 13.3 CAN Protocol 13.3 CAN Protocol 13.3.1 CAN Protocol Frames Following four types of frames are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Each frame is separated by an interframe space. Data frame Standard format 0~64...
Page 615 CAN MODULES 13.3 CAN Protocol Error frame 6~12 Interframe space or Error flag Error delimiter overload flag Overload frame 6~12 Interframe space or Overload flag overload flag Overload delimiter Interfame space For error-active state SOF of the next frame Bus idle Intermission For error-passive state SOF of the next frame...
Page 616 CAN MODULES 13.3 CAN Protocol Initial setting Error-active state Transmit error counter ≥ 128 11 consecutive recessive bits detected on CAN bus 128 times Receive error counter ≥ 128 reset in software Transmit error counter < 128 Receive error counter < 128 Error-passive Bus-off state state...
Page 617: Initialization Of The Can Module
CAN MODULES 13.4 Initialization of the CAN Module 13.4 Initialization of the CAN Module 13.4.1 Initializing the CAN Module Before performing communication, set up the CAN module following the procedure described below. (1) Selecting pin functions The CAN transmit data output pins (CTX0 and CTX1) are shared with input/output ports performing dual functions.
Page 618 CAN MODULES 13.4 Initialization of the CAN Module 1 Bit Synchronization Propagation Segment Phase Segment1 Phase Segment2 Segment Sampling Point • This diagram shows bit timing when one bit is comprised of 8 Tq's. • When chosen to sample once, the value sampled at Sampling Point (1) is assumed to be the value of the bit.
Page 619 CAN MODULES 13.4 Initialization of the CAN Module CAN module initialization Set input/output port operation mode register Set interrupt controller Set interrupt priority level Settings of CAN error Settings of CAN slot interrupt mask registers interrupt mask registers • Enable/disable CAN •...
Page 620: Can Timing
CAN MODULES 13.4 Initialization of the CAN Module 13.4.2 CAN Timing The CAN modules incorporated in the M32R/E sample the asynchronous input signal on the CRX pin with a Tq clock period that is the base clock. The sampled signal is assumed to be the CAN bus value.
Page 621: Transmitting Data Frames
CAN MODULES 13.5 Transmitting Data Frames 13.5 Transmitting Data Frames 13.5.1 Data Frame Transmission Procedure The following shows the procedure for transmitting a data frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot from which to transmit by writing H'00 to the register.
Page 622 CAN MODULES 13.5 Transmitting Data Frames Data frame transmission procedure Initialize CAN message slot Write H'00 control register Read CAN message slot control register Verify that transmission is idle TRSTAT bit = 0 Set ID and data in message slot Set extended ID register Standard ID or extended ID Set CAN message slot...
Page 623: Data Frame Transmit Operation
CAN MODULES 13.5 Transmitting Data Frames 13.5.2 Data Frame Transmit Operation The following describes how data frame transmit operation is performed. All these operations are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots for which there is a transmit request (including remote frame transmit slots) every intermission to determine the frame to transmit.
Page 624: Transmit Abort Function
CAN MODULES 13.5 Transmitting Data Frames B'0000 0000 (Note) Write H'80 Transmit abort Transmit wait B'1000 0000 state Accept transmit Failed in arbitration request or CAN bus error occurs Transmit abort B'0000 0010 B'1000 0010 Finish transmitting B'0000 0001 B'1000 0001 (Note) Note: When in this state, the message slot can be accessed for write.
Page 625: Receiving Data Frames
CAN MODULES 13.6 Receiving Data Frames 13.6 Receiving Data Frames 13.6.1 Data Frame Reception Procedure The following describes the procedure for receiving a data frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot in which to receive by writing H'00 to the register.
Page 626 CAN MODULES 13.6 Receiving Data Frames Data frame reception procedure Initialize CAN message slot Write H'00 control register Read CAN message slot control register Verify that reception is idle TRSTAT bit = 0 Set ID in message slot Standard ID or extended ID Set extended ID register Set CAN message slot Write H'40 (receive request)
Page 627: Data Frame Receive Operation
CAN MODULES 13.6 Receiving Data Frames 13.6.2 Data Frame Receive Operation The following describes how data frame receive operation is performed. All these operations are automatically performed in hardware. (1) Acceptance filtering When data reception is completed, the CAN module searches for slots sequentially from slot 0 (up to slot 15) that meet the receive conditions and are therefore eligible for the received message.
Page 628 CAN MODULES 13.6 Receiving Data Frames B'0000 0000 Set receive request Clear receive request Wait for received data B'0100 0000 Store received data Clear receive request B'0000 0011 B'0100 0011 Finish storing Finish storing received data received data Clear receive request B'0100 0001 B'0000 0001 Store received data...
Page 629: Reading Out A Received Data Frame
CAN MODULES 13.6 Receiving Data Frames 13.6.3 Reading Out a Received Data Frame The following shows the procedure for reading a received data frame from the slot. (1) Clearing the TRFIN (transmit/receive finished) bit Clear the CAN Message Slot Control Register (CMSLnCNT)'s TRFIN (transmit/receive finished) bit to 0 by writing H'4E, H'40, or H'00 to the register.
Page 630 CAN MODULES 13.6 Receiving Data Frames Reading out received data Clear TRFIN bit to 0 Write H'4E, H'40, or H'00 Read data from message slot Read CAN message slot control register TRFIN bit = 0 Finished reading out received data Figure 13.6.3 Procedure for Reading Out Received Data 13-94...
Page 631: Transmitting Remote Frames
CAN MODULES 13.7 Transmitting Remote Frames 13.7 Transmitting Remote Frames 13.7.1 Remote Frame Transmission Procedure The following shows the procedure for transmitting a remote frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot from which to transmit by writing H'00 to the register.
Page 632 CAN MODULES 13.7 Transmitting Remote Frames Remote frame transmission procedure Initialize CAN message slot Write H'00 control register Read CAN message slot control register Verify that transmission is idle TRSTAT bit = 0 Set ID in message slot Set extended ID register Standard ID or extended ID Set CAN message slot Write H'A0 (transmit request, remote)
Page 633: Remote Frame Transmit Operation
CAN MODULES 13.7 Transmitting Remote Frames 13.7.2 Remote Frame Transmit Operation The following describes how remote frame transmit operation is performed. All these operations are automatically performed in hardware. (1) Setting the RA (remote active) bit The RA (remote active) bit that indicates that the slot is selected to handle a remote frame is set to 1 at the same time the data H'A0 (transmit request, remote) is written to the CAN Message Slot Control Register.
Page 634 CAN MODULES 13.7 Transmitting Remote Frames (7) Acceptance filtering When data reception is completed, the CAN module searches for slots sequentially from slot 0 (up to slot 15) that meet the receive conditions and are therefore eligible for the received message. The following shows the receive conditions for the slots that have been set to receive a data frame.
Page 635 CAN MODULES 13.7 Transmitting Remote Frames B'0000 0000 Store the received Clear transmit data request B'0000 1000 B'1010 1000 B'1010 1011 B'0000 1011 Finish storing Finish storing CAN bus error the received data the received data occurs Clear transmit request B'1010 1010 B'0000 1010 B'0000 0001...
Page 636: Reading Out A Received Data Frame When Set For Remote Frame Transmission
CAN MODULES 13.7 Transmitting Remote Frames 13.7.3 Reading Out a Received Data Frame When Set for Remote Frame Transmission The following shows the procedure for reading a received data frame from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (transmit/receive finished) bit Clear the CAN Message Slot Control Register (CMSLnCNT)'s TRFIN (transmit/receive finished) bit to 0 by writing H'AE or H'00 to the register.
Page 637 CAN MODULES 13.7 Transmitting Remote Frames Reading out received data Write H'AE or H'00 Clear TRFIN bit to 0 Read data from message slot Read CAN message slot control register TRFIN bit = 0 Finished reading out received data Figure 13.7.3 Procedure for Reading Out Received Data When Set for Remote Frame Transmission 13-101...
Page 638: Receiving Remote Frames
CAN MODULES 13.8 Receiving Remove Frames 13.8 Receiving Remote Frames 13.8.1 Remote Frame Reception Procedure The following describes the procedure for receiving a remote frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot in which to receive by writing H'00 to the register.
Page 639 CAN MODULES 13.8 Receiving Remove Frames Remote frame reception procedure Initialize CAN message slot Write H'00 control register Read CAN message slot control register Verify that reception is idle TRSTAT bit = 0 Set ID in message slot Set extended ID register Standard ID or extended ID Set CAN message slot Write H'60 (receive request, remote, automatic answering enabled)
Page 640: Remote Frame Receive Operation
CAN MODULES 13.8 Receiving Remove Frames 13.8.2 Remote Frame Receive Operation The following describes how remote frame receive operation is performed. All these operations are automatically performed in hardware. (1) Setting the RA (remote active) bit The RA (remote active) bit that indicates that the slot is selected to handle a remote frame is set to 1 at the same time the data H'60 (receive request, remote) or H'70 (receive request, remote, automatic answering disabled) is written to the CAN Message Slot Control Register.
Page 641 CAN MODULES 13.8 Receiving Remove Frames (5) Operation after receiving a remote frame The operation to be performed for the slot after receiving a remote frame differs depending on whether automatic answering is enabled or not. When automatic answering is disabled The slot which finished receiving data becomes inactive and remains idle (neither transmitting nor receiving) until new settings are made for it in software.
Page 642 CAN MODULES 13.8 Receiving Remove Frames B'0000 0000 Write H'60 Write H'70 (automatic answering (automatic answering disabled) enabled) Clear receive request Wait for reception B'0110 1000 B'0111 1000 Store the received Store the data received data Store the received data Store the received data Clear receive request Clear receive request...
Page 643: Chapter 14 Real-Time Debugger (Rtd)
CHAPTER 14 CHAPTER 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.2 Pin Function of the RTD 14.3 Functional Description of the RTD 14.4 Typical Connection with the Host...
Page 644 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.1 Outline of the Real-Time Debugger (RTD) The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU.
Page 645 REAL-TIME DEBUGGER (RTD) 14.2 Pin Function of the RTD 14.2 Pin Function of the RTD Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input...
Page 646: Outline Of Rtd Operation
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3 Functional Description of the RTD 14.3.1 Outline of RTD Operation Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19(note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data Command Mnemonic...
Page 647: Operation Of Rdr (Real-Time Ram Content Output)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.2 Operation of RDR (Real-time RAM Content Output) When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop.
Page 648 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD (LSB side) (MSB side) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • RTDTXD Read data (Note) Note: The read data is transferred LSB-first.
Page 649: Operation Of Wrr (Ram Content Forcible Rewrite)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU.
Page 650 REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM).
Page 651: Operation Of Ver (Continuous Monitor)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.4 Operation of VER (Continuous Monitor) When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command.
Page 652: Operation Of Vei (Interrupt Request)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.5 Operation of VEI (Interrupt Request) When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command.
Page 653: Operation Of Rcv (Recover From Runaway)
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.6 Operation of RCV (Recover from Runaway) When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession.
Page 654: Method To Set A Specified Address When Using The Rtd
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.7 Method to Set a Specified Address when Using the RTD When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses of that area.
Page 655: Resetting The Rtd
REAL-TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.8 Resetting the RTD The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after System Reset Pin Name State...
Page 656: Typical Connection With The Host
REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host 14.4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. Host M32R/E microprocessor...
Page 657 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally.
Page 658 REAL-TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host * This is a blank page.* 14-16 Rev.1.0...
Page 659: Chapter 15 Pd Module
CHAPTER 15 CHAPTER 15 PD MODULE 15.1 Outline of the PD Module 15.2 PD Module Related Regis ters 15.3 Initialization for PD Sensor Support 15.4 Precautions on Using the PD Module...
Page 660 15.1 Outline of the PD Module 15.1 Outline of the PD Module The 32172/32173 contains eight channels of event counters that can be used as a dedicated interface circuit for PD (Phase Digital) sensors. Combined with PD sensors, the PD module can perform predictive computations at high speed that are required during position detection.
Page 661 PD MODULE 15.1 Outline of the PD Module Table 15.1.3 PD Module DMA Transfer Request Generation Function DMA transfer request generation function DMA input channel PD0_ABD compare match Channels 1-9 PD0_ABD&PITCH compare match (note) PD1_ABD compare match Channels 1-9 PD1_ABD&PITCH compare match (note) TIN0A input detection Channels 0 TIN0B input detection...
Page 662 PD MODULE 15.1 Outline of the PD Module Converter Reload Register Internal peripheral DACNT PRSA clock (BCLK) DPRAM 256 bytes R-2R Internal peripheral PRSB clock (BCLK) DRQ23 IRQ31 TPDMR0 TIN0AS TIN0AS Pnew0 TPDMR1 IRQ31 Pold0 DRQ24 IRQ2 IRQ31 DRQ21 TIN0BS TIN0BS TPDMR2 Mnew0...
Page 663 PD MODULE 15.2 PD Module Related Registers 15.2 PD Module Related Registers A PD module related register map is shown below. Address +0 address +1 address D7 D8 H'0080 1800 Prescaler Register A (PRSA) Prescaler Register B (PRSB) H'0080 1802 DACNT Reload Register (DACNTRL) TIN Input Processing Control Register (TINPDCR) H'0080 1804...
Page 664 PD MODULE 15.2 PD Module Related Registers Address +0 address +1 address D7 D8 H'0080 1880 Prescaler Register 1C(PRS1C) SMSB Control Register 1(SMSBCR1) H'0080 1882 TEP1M Control Register (TEP1MCR) TEP1P Control Register (TEP1PCR) H'0080 1884 TEP1P Counter (TEP1PCT) H'0080 1886 TEP1M Counter (TEP1MCT) H'0080 1888 PD1 Data Updating Disable Event Select Register (PDNSEL1R) PD1 Data Updating Control Register (PDNCNT1R)
Page 665: Prescaler Unit
PD MODULE 15.2 PD Module Related Registers 15.2.1 Prescaler Unit The prescalers PRSA, PRSB, PRS0C, and PRS1C each consist of an 8-bit counter which generates clocks from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) for supply to each timer.
Page 666 PD MODULE 15.2 PD Module Related Registers Prescaler Register B (PRSB) <Address: H'0080 1801> PRSB <When reset: H'00> Bit Name Function 8-15 PRSB Sets the prescaler's divide-by value The Prescaler B generates a count clock for the 16-bit input measure counter (TPDCT) from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value.
Page 667 PD MODULE 15.2 PD Module Related Registers Prescaler Register 0C (PRS0C) <Address: H'0080 1840> Prescaler Register 1C (PRS1C) <Address: H'0080 1880> PRS0C, PRS1C <When reset: H'00> Bit Name Function PRS0C, PRS1C Sets the prescaler's divide-by value These prescalers generate count clocks for the TEPiP and TEPiM counters from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value.
Page 668: Dacnt Reload Register
PD MODULE 15.2 PD Module Related Registers 15.2.2 DACNT Reload Register DACNT Reload Register (DACNTRL) <Address: H'0080 1802> DACNTRL <When reset: H'00> Bit Name Function DACNTRL 8-bit reload register value The DACNT Reload Register is used to reload data into the DACNT Counter. Data is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed.
Page 669: Tin Input Processing Control Register
PD MODULE 15.2 PD Module Related Registers 15.2.3 TIN Input Processing Control Register TIN Input Processing Control Register (TINPDCR) <Address: H'0080 1803> TIN1BS TIN1AS TIN0BS TIN0AS <When reset: H'00> Bit Name Function TIN1BS 00: Input has no effect (Select TIN1BS input processing) 01: Rising edge 10: Falling edge 11: Both edges 10-11...
Page 670 PD MODULE 15.2 PD Module Related Registers Count clock Figure 15.2.3 Rising Edge Detection Count clock Figure 15.2.4 Falling Edge Detection Count clock Figure 15.2.5 Both Edge Detection 15-12 Rev.1.0...
Page 671: Tin Interrupt Control Register
PD MODULE 15.2 PD Module Related Registers 15.2.4 TIN Interrupt Control Register TIN Interrupt Control Register (TINPDICR) <Address: H'0080 1804> TIN1BEIM TIN1AEIM TIN0BEIM TIN0AEIM TIN1BIM TIN1AIM TIN0BIM TIN0AIM <When reset: H'00> Bit Name Function TIN1BEIM (Note) 0: Disables interrupt TIN1AEIM (Note) 1: Enables interrupt TIN0BEIM (Note) TIN0AEIM (Note)
Page 672: Tin Interrupt Status Register
PD MODULE 15.2 PD Module Related Registers 15.2.5 TIN Interrupt Status Register TIN Interrupt Status Register (TINPDIST) <Address: H'0080 1805> TIN1BEIS TIN1AEIS TIN0BEIS TIN0AEIS TIN1BIS TIN1AIS TIN0BIS TIN0AIS <When reset: H'00> Bit Name Function TIN1BEIS 0: Interrupt not requested TIN1AEIS 1: Interrupt requested TIN0BEIS TIN0AEIS...
Page 673 PD MODULE 15.2 PD Module Related Registers TINPD1CR <H'0080 1804> TINPD2CR <H'0080 1805> TIN1BEedge Data bus 8-source inputs TIN1BEIS PDC input interrupt IRQ31 (Level) TIN1BEIM TINAE1edge TIN1AEIS TIN1AEIS TIN0Bedge TIN0BEIS TIN0BEIM TIN0Aedge TIN0AEIS TIN0AEIM TIN1Bedge TIN1BIS TIN1BIM TIN1Aedge TIN1AIS TIN1AIM TIN0Bedge TIN0BIS TIN0BIM...
Page 674: Dacnt Control Register
PD MODULE 15.2 PD Module Related Registers 15.2.6 DACNT Control Register DACNT Control Register (DACNTCR) <Address: H'0080 1806> DACNTEN <When reset: H'00> Bit Name Function No functions assigned – DACNTEN 0: Stops count (DACNT count enable) 1: Enables count This register controls enabling/disabling of the DACNT Counter to or not to count. When the DACNTEN bit is set to 1, the DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA.
Page 675: Tpd Control Register
PD MODULE 15.2 PD Module Related Registers 15.2.7 TPD Control Register TPD Control Register (TPDCR) <Address: H'0080 1807> TPDMD TPDEN <When reset: H'00> Bit Name Function 8-10 No functions assigned – TPDMD 0: Normal mode (TPD counter operation mode) 1: PD sensor support mode 12-14 No functions assigned –...
Page 676: Dacnt Counter
PD MODULE 15.2 PD Module Related Registers 15.2.8 DACNT Counter DACNT Counter (DACNT) <Address: H'0080 1808> DACNT <When reset: H'0000> Bit Name Function DACNT 8-bit counter value The DACNT Counter is an 8-bit down-counter which after being enabled, starts counting down from its set value synchronously with the count clock generated by the PRSA.
Page 677: Tpd Counter
PD MODULE 15.2 PD Module Related Registers 15.2.9 TPD Counter TPD Counter (TPDCT) <Address: H'0080 180E> 14 D15 TPDCT <When reset: H'0000> Bit Name Function 0-15 TPDCT 16-bit counter value The TPD Counter is a 16-bit up-counter which after being enabled, starts counting up from its set value synchronously with the count clock generated by the PRSB (free-running counter).
Page 678: Tpd Measure Registers
PD MODULE 15.2 PD Module Related Registers 15.2.10 TPD Measure Registers TPD Measure Register 0 (TPDMR0) <Address: H'0080 1810> TPD Measure Register 1 (TPDMR1) <Address: H'0080 1812> TPD Measure Register 2 (TPDMR2) <Address: H'0080 1814> TPD Measure Register 3 (TPDMR3) <Address: H'0080 1816>...
Page 679 PD MODULE 15.2 PD Module Related Registers The following shows a typical operation of TPD measure inputs. Enabled TIN1A TIN1B TIN0A TIN0B TIN0A TIN0B TIN1A TIN1B event event event event event event event event occurs occurs occurs occurs occurs occurs occurs occurs Enable bit...
Page 680: Pd Calculation Interrupt Control Register
PD MODULE 15.2 PD Module Related Registers 15.2.11 PD Calculation Interrupt Control Register PD Calculation Interrupt Control Register (PDICR) <Address: H'0080 1830> APCM1IM SER1IM PCM1IM ACM1IM APCM0IM SER0IM PCM0IM ACM0IM <When reset: H'00> Bit Name Function APCM1IM 0: Disables interrupt SER1IM 1: Enables interrupt PCM1IM...
Page 681: Pd Calculation Interrupt Status Register
PD MODULE 15.2 PD Module Related Registers 15.2.12 PD Calculation Interrupt Status Register PD Calculation Interrupt Status Register (PDIST) <Address: H'0080 1831> APCM1IS SER1IS PCM1IS ACM1IS APCM0IS SER0IS PCM0IS ACM0IS <When reset: H'00> Bit Name Function APCM1IS 0: Interrupt not requested SER1IS 1: Interrupt requested PCM1IS...
Page 682 PD MODULE 15.2 PD Module Related Registers PDICR <H'0080 1830> PDIST <H'0080 1831> APCM1edge Data bus 8-source inputs APCM1IS PD calculation interrupt APCM1IM (Level) IRQ2 SER1edge SER1IS SER1IM PCM1edge PCM1IS PCM1IM ACM1edge ACM1IS ACM1IM APCM0edge APCM0IS APCM0IM SER0edge SER0IS SER0IM PCM0edge PCM0IS PCM0IM...
Page 683: Position Detection Accuracy Select Register
PD MODULE 15.2 PD Module Related Registers 15.2.13 Position Detection Accuracy Select Register Position Detection Accuracy Select Register (PDASR) <Address: H'0080 1832> <When reset: H'00> Bit Name Function No functions assigned – 2'b00: 10-bit accuracy (Select position detection 2'b01: 11-bit accuracy accuracy) 2'b10: 12-bit accuracy 2'b11: Use inhibited...
Page 684: Tep Control Registers
PD MODULE 15.2 PD Module Related Registers 15.2.14 TEP Control Registers TEP0P Control Register (TEP0CR) <Address: H'0080 1842> TEP1P Control Register (TEP1CR) <Address: H'0080 1882> TEP0PM, TEP0PEN, TEP1PM TEP1PEN <When reset: H'00> Bit Name Function No functions assigned – TEP0PM, TEP1PM 0: Event count mode (Operation mode) 1: PD sensor support mode...
Page 685 PD MODULE 15.2 PD Module Related Registers TEP0M Control Register (TEP0MCR) <Address: H'0080 1843> TEP1M Control Register (TEP1MCR) <Address: H'0080 1883> TEP0MM, TEP0MEN, TEP1MM TEP1MEN <When reset: H'00> Bit Name Function 8-10 No functions assigned – TEP0MM, TEP1MM 0: Event count mode (Operation mode) 1: PD sensor support mode 12-14...
Page 686: Tep Counters
PD MODULE 15.2 PD Module Related Registers 15.2.15 TEP Counters TEP0P Counter (TEP0PCT) <Address: H'0080 1844> TEP1P Counter (TEP1PCT) <Address: H'0080 1884> TEP0M Counter (TEP0MCT) <Address: H'0080 1846> TEP1M Counter (TEP1MCT) <Address: H'0080 1886> 14 D15 TEP0P, TEP1P, TEP0M, TEP1M <When reset: H'00>...
Page 687 PD MODULE 15.2 PD Module Related Registers (1) Event count mode The counter counts up each time an event input on the corresponding TIN pin is detected. TIN0A TIN0B TIN1A TIN1B TIN0A TIN0B TIN1A TIN1B event event event event event event event event...
Page 688: Pd Data Updating Disable Event Select Registers
PD MODULE 15.2 PD Module Related Registers 15.2.16 PD Data Updating Disable Event Select Registers PD0 Data Updating Disable Event Select Register (PDNSEL0R) <Address: H'0080 1848> PD1 Data Updating Disable Event Select Register (PDNSEL1R) <Address: H'0080 1888> PDNSEL0,PDNSEL1 <When reset: H'00> Bit Name Function No functions assigned...
Page 689: Pd Data Updating Control Registers
PD MODULE 15.2 PD Module Related Registers 15.2.17 PD Data Updating Control Registers PD0 Data Updating Control Register (PDNCNT0R) <Address: H'0080 1849> PD1 Data Updating Control Register (PDNCNT1R) <Address: H'0080 1889> PDNCNT0,PDNCNT1 <When reset: H'00> Bit Name Function 8-13 No functions assigned –...
Page 690: Abd Mask Registers
PD MODULE 15.2 PD Module Related Registers 15.2.18 ABD Mask Registers ABD0 Mask Register (ABD0MK) <Address: H'0080 184A> ABD1 Mask Register (ABD1MK) <Address: H'0080 188A> ABD0MK, ABD1MK <When reset: H'00> Bit Name Function ABD0MK, ABD1MK 0: Mask (ABD compare match mask) 1: Compare When comparing the ABDiLT Register and ABDi Compare Register values to determine whether they match, this register may be used to mask the low-order bits of the comparison result.
Page 691: S Error Detection Range Select Registers
PD MODULE 15.2 PD Module Related Registers 15.2.19 S Error Detection Range Select Registers S Error 0 Detection Range Select Register (SNEW0MK) <Address: H'0080 184B> S Error 1 Detection Range Select Register (SNEW1MK) <Address: H'0080 188B> ABD0MK, ABD1MK <When reset: H'00> Bit Name Function 8-15...
Page 692: Abd Compare Registers
PD MODULE 15.2 PD Module Related Registers 15.2.20 ABD Compare Registers ABD0 Compare Register (ABD0CM) <Address: H'0080 184C> ABD1 Compare Register (ABD1CM) <Address: H'0080 188C> 14 D15 ABD0MK, ABD1MK <When reset: H'0000> Bit Name Function No functions assigned – ABD0CM, ABD1CM 12-bit compare value The value set in this register is compared with the ABDiLT Register value and when they match, an ABD compare match interrupt request is set.
Page 693: Pitch Compare Registers
PD MODULE 15.2 PD Module Related Registers 15.2.21 PITCH Compare Registers PITCH0 Compare Register (PITCH0CMR) <Address: H'0080 184E> PITCH1 Compare Register (PITCH1CMR) <Address: H'0080 188E> 14 D15 PIT0CM, PIT1CM <When reset: H'0000> Bit Name Function 0-15 PIT0CM, PIT1CM 16-bit compare value The value set in this register is compared with the PITCHi Counter Register value and when they match, a PITCH compare match interrupt request is set.
Page 694: Fdlt Registers
PD MODULE 15.2 PD Module Related Registers 15.2.22 FDLT Registers FDLT0 Register (FDLT0) <Address: H'0080 1872> FDLT1 Register (FDLT1) <Address: H'0080 18B2> 14 D15 FD0, FD1 <When reset: H'0000> Bit Name Function 0-11 FD0, FD1 12-bit FD value – 12-15 No functions assigned –...
Page 695: Pitchlt Registers
PD MODULE 15.2 PD Module Related Registers 15.2.23 PITCHLT Registers PITCHLT0 Register (PITCHLT0) <Address: H'0080 1874> PITCHLT1 Register (PITCHLT1) <Address: H'0080 18B4> 14 D15 PITCH0, PITCH1 <When reset: H'0000> Bit Name Function 0-15 PITCH0, PITCH1 16-bit PITCH counter value Note 1: This register must always be accessed in halfwords. Note 2: When performing predictive calculations, access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction.
Page 696: Abdlt Registers
PD MODULE 15.2 PD Module Related Registers 15.2.24 ABDLT Registers ABDLT0 Register (ABDLT0) <Address: H'0080 1876> ABDLT1 Register (ABDLT1) <Address: H'0080 18B6> 14 D15 ABD0, ABD1 <When reset: H'0000> Bit Name Function 0-15 ABD0, ABD1 12-bit ABD value – Note 1: This register must always be accessed in halfwords. Note 2: When performing predictive calculations, access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction.
Page 697: Rsumlt Registers
PD MODULE 15.2 PD Module Related Registers 15.2.25 RSUMLT Registers RSUMLT0 Register (RSUMLT0) <Address: H'0080 1878> RSUMLT1 Register (RSUMLT1) <Address: H'0080 18B8> 14 D15 RSUM0, RSUM1 <When reset: H'0000> Bit Name Function 0-15 RSUM0, RSUM1 16-bit correction factor – Note: This register must always be accessed as signed halfword data This register is used to store the correction factor necessary for predictive calculations.
Page 698: Sslt Registers
PD MODULE 15.2 PD Module Related Registers 15.2.26 SSLT Registers SSLT0 Register (SSLT0) <Address: H'0080 187A> SSLT1 Register (SSLT1) <Address: H'0080 18BA> 14 D15 SSLT0, SSLT1 <When reset: H'0000> Bit Name Function 0-11 SSLT0, SSLT1 12-bit SSLT value – 12-15 No functions assigned –...
Page 699 PD MODULE 15.3 Initialization for PD Sensor Support 15.3 Initialization for PD Sensor Support When using the PD module in combination with PD sensors, follow the initialization procedure described below to initialize it. (1) Setting the Input/output Port Operation Mode Register The TINA0, TENB0, TINA1, and TENB1 pins are dual-function pins shared with input/output ports each.
Page 700 PD MODULE 15.3 Initialization for PD Sensor Support (7) Setting the PD related registers • Setting the Prescalers 0C and 1C Always write the value H'00 in these registers. • Setting the PD0 and PD1 Data Updating Disable Event Select Registers Use these registers to set data-updating disable events.
Page 701: Initialization For Pd Sensor Support
PD MODULE 15.3 Initialization for PD Sensor Support (11) Setting the TEP0P, TEP0M, TEP1P, and TEP1M Control Registers Set the value H'11 in each register to enable counting in PD sensor support mode. Note: Use all of the data tables 0-255 to define the sine wave. (12) Setting the TIN Input Processing Control Register Select rising-edge detection for each TIN input.
Page 702: Precautions On Using The Pd Module
PD MODULE 15.4 Precautions on Using the PD Module 15.4 Precautions on Using the PD Module • PD calculation processing is always performed based on the latest measured value regardless of how the PDi Data Updating Control Register is set. Therefore, even after disabling data updating, it is possible to read out the calculation result based on the latest event input by altering register settings back again.
Page 703: Chapter 16 D-A Converters
CHAPTER 16 CHAPTER 16 D-A CONVERTERS 16.1 Outline of the D-A Converters 16.2 D-A Converter Related Registers 16.3 Functional Description of the D-A Converters...
Page 704 D-A CONVERTERS 16.1 Outline of the D-A Converters 16.1 Outline of the D-A Converters The 32172/32173 contains two 8-bit D-A converters (D-A0 and D-A1 Converters). D-A conversion is performed in either single mode or continuous mode (D-A0 Converter only). Single mode: The analog values corresponding to the D-A Converter Register (DA0CNV, DA1CNV) values are output from the DA0 and DA1 pins.
Page 705 D-A CONVERTERS 16.1 Outline of the D-A Converters Internal Data Bus PD Module BCLK PRSA DA Counter (DACNT) (TPD reset) D-A0 Data Register 0 D-A0 Conversion Register 256 bytes Single mode D-A0 Data Register 255 Continuous mode DA0ON DA0/(AD1IN4) 8-bit R-2R Resistor Ladder AD1IN4 Figure 16.1.1 Block Diagram of the D-A0 Converter Internal Data Bus...
Page 706 D-A CONVERTERS 16.1 Outline of the D-A Converters DA0 analog output enable bit "0" "1" D-A0 Conversion Register "0" "1" AVSS VREF Note 1: This applies to the case where the value of the D-A0 Conversion Register is H'2A. Note 2: This circuit is the same as for the D-A1 Converter. Note 3: When not using the D-A converters, set the D-A Control Register's analog output enable bit (DA0ON, DA1ON) to 0 and write the data H'00 to the D-A Conversion Register (DA0CNV, DA1CNV) to prevent current from flowing into the R-2R resistors.
Page 707: D-A Converter Related Registers
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2 D-A Converter Related Registers A D-A converter related register map is shown below. +0 address +1 address Address D7 D8 Prescaler Register A (PRSA) H'0080 1800 H'0080 1802 DACNT Reload Register (DACNTRL) H'0080 1804 H'0080 1806 DACNT Control Register (DACNTCR)
Page 708 D-A CONVERTERS 16.2 D-A Converter Related Registers Address +0 address +1 address D7 D8 H'0080 1D50 D-A0 Data Register 80 (DA0DT80) D-A0 Data Register 81 (DA0DT81) H'0080 1D52 D-A0 Data Register 82 (DA0DT82) D-A0 Data Register 83 (DA0DT83) H'0080 1D54 D-A0 Data Register 84 (DA0DT84) D-A0 Data Register 85 (DA0DT85) H'0080 1D56...
Page 709 D-A CONVERTERS 16.2 D-A Converter Related Registers Address +0 address +1 address D7 D8 H'0080 1DAA D-A0 Data Register 170 (DA0DT170) D-A0 Data Register 171 (DA0DT171) H'0080 1DAC D-A0 Data Register 172 (DA0DT172) D-A0 Data Register 173 (DA0DT173) H'0080 1DAE D-A0 Data Register 174 (DA0DT174) D-A0 Data Register 175 (DA0DT175) H'0080 1DB0...
Page 710: Prescaler Unit
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.1 Prescaler Unit The Prescaler PRSA consists of an 8-bit counter which generates a clock from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) for supply to the DACNT Counter. The prescaler value is initialized to H'00 when reset.
Page 711 D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.2 DACNT Reload Register DACNT Reload Register (DACNTRL) <Address: H'0080 1802> DACNTRL <When reset: H'00> Bit Name Function DACNTRL 8-bit reload register value The DACNT Reload Register is used to reload data into the DACNT Counter. Data is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed.
Page 712: Dacnt Control Register
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.3 DACNT Control Register DACNT Control Register (DACNTCR) <Address: H'0080 1806> DACNTEN <When reset: H'00> Bit Name Function No functions assigned – DACNTEN 0: Stops count 1: Enables count This register controls enabling/disabling of the DACNT Counter to or not to count. When the DACNTEN bit is set to 1, the DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA.
Page 713: Dacnt Reload Register
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.4 DACNT Counter DACNT Counter (DACNT) <Address: H'0080 1808> DACNT <When reset: H'00> Bit Name Function DACNT 8-bit counter value The DACNT Counter is an 8-bit down-counter which after being enabled, starts counting down from its set value synchronously with the count clock generated by the PRSA.
Page 714: D-A Control Register
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.5 D-A Control Register D-A Control Register (DACR) <Address: H'0080 1C7C> DA0MOD DA1ON DA0ON <When reset: H'00> Bit Name Function No functions assigned – DA0MO 0: Single mode (Select DA0 mode) 1: Continuous mode DA1ON 0: Disables output (Enable DA1 analog output)
Page 715: D-A Conversion Registers
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.6 D-A Conversion Registers D-A0 Conversion Register (DA0CNV) <Address: H'0080 1C78> D-A1 Conversion Register (DA1CNV) <Address: H'0080 1C7A> DA0CNV, DA1CNV <When reset: H'00> Bit Name Function DA0CNV, DA1CNV 8-bit D-A conversion data (single mode) Writing a value (0-255) to the D-A Conversion Register (DA0CNV, DA1CNV) causes D-A conversion to start.
Page 716: D-A0 Data Registers
D-A CONVERTERS 16.2 D-A Converter Related Registers 16.2.7 D-A0 Data Registers D-A0 Data Register n (DA0DTn) <Address: H'0080 1D00 to H'0080 1DFF> D15) DA0DTn <When reset: indeterminate> Bit Name Function DA0DTn 8-bit D-A conversion data (continuous mode) The D-A0 Data Registers n (n = 0-255) are used for D-A conversion in continuous mode. The values set in the D-A0 Data Registers are sequentially D-A converted and output as analog quantities.
Page 717: Functional Description Of The D-A Converters
D-A CONVERTERS 16.3 Functional Description of the D-A Converters 16.3 Functional Description of the D-A Converters D-A conversion is performed in either single or continuous mode (the latter for only the D-A0 Converter). 16.3.1 Single Mode In this mode, an analog value corresponding to the value set in the D-A Conversion Register (DAiCNV) is output from the external pin DAi.
Page 718 D-A CONVERTERS 16.3 Functional Description of the D-A Converters *** This is a blank page *** 16-16 Rev.1.0...
Page 719: Chapter 17 External Bus Interface
CHAPTER 17 CHAPTER 17 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals 17.2 Read/Write Operations 17.3 Bus Arbitration 17.4 Example for Connecting External Extension Memory...
Page 720 17.1 External Bus Interface Related Signals 17.1 External Bus Interface Related Signals The 32172/32173 has the signals listed below that are associated with the external bus interface. These signals can be used in external extended mode or processor mode. (1) Address The external bus interface outputs 19-bit address (A12-A30) for addressing a 1-Mbyte space.
Page 721 ____ (8) Wait (WAIT) When the 32172/32173 started an external bus cycle, it automatically inserts wait cycles while ____ the WAIT signal is asserted. For details, see Chapter 18, "Wait Controller." When not using the WAIT function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0.
Page 722 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals ____ HACK pin outputs a low-level signal during hold and while going to a hold state. To return from ____ the hold state to a normal operating state, release the HREQ input signal back high. When not using the HREQ and HACK functions, these pins can be used as P72 and P73 by setting the P7 Operation Mode Register P72MOD and P73MOD bits to 0.
Page 723 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals (10) Port operation mode register When the CPU is set to operate in external extended or processor mode, ports P0-P4 and P22 have their functions changed to signal pins for external access. When reset, these pins handle port signals.
Page 724 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P1 Operation Mode Register (P1MOD) <Address: H'0080 0741> P10MOD P11MOD P12MOD P13MOD P14MOD P15MOD P16MOD P17MOD <When reset: H'00> Bit Name Function P10MOD 0: DB8 (Port P10 operation mode) 1: P10 P11MOD 0: DB9 (Port P11 operation mode)
Page 725 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P2 Operation Mode Register (P2MOD) <Address: H'0080 0742> P20MOD P21MOD P22MOD P23MOD P24MOD P25MOD P26MOD P27MOD <When reset: H'00> Bit Name Function P20MOD 0: A23 (Port P20 operation mode) 1: P20 P21MOD 0: A24 (Port P21 operation mode)
Page 726 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P3 Operation Mode Register (P3MOD) <Address: H'0080 0743> P30MOD P31MOD P32MOD P33MOD P34MOD P35MOD P36MOD P37MOD <When reset: H'00> Bit Name Function P30MOD 0: A15 (Port P30 operation mode) 1: P30 P31MOD 0: A16 (Port P31 operation mode)
Page 727 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P4 Operation Mode Register (P4MOD) <Address: H'0080 0744> P41MOD P42MOD P43MOD P44MOD P45MOD P47MOD <When reset: H'00> Bit Name Function No functions assigned – _______ ______ P41MOD 0: BLW/BLE (Port P41 operation mode) 1: P41 _______ ______...
Page 728 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset: H'00> Bit Name Function P70MOD 0: P70 (Port P70 operation mode) 1: BCLK/WR P71MOD 0: P71 ____...
Page 729 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> P220MOD P225MOD <When reset: H'00> Bit Name Function P220MOD 0: P220 (Port P220 operation mode) 1: CTX0 No functions assigned – P225MOD 0: P225 (Port P225 operation mode) 1: Use inhibited No functions assigned...
Page 730 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals P4 Peripheral Output Select Register (P4SMOD) <Address: H'0080 0764> P46SMOD <When reset: H'00> Bit Name Function No functions assigned – P46SMOD 0: A13 _______ (Select port P46 peripheral output) 1: CS3 No functions assigned –...
Page 731 EXTERNAL BUS INTERFACE 17.1 External Bus Interface Related Signals (11) Bus Mode Control Register (BUSMODC) The microcomputer contains a function to select between two external bus modes. Bus Mode Control Register (BUSMODC) <Address: H'0080 077F> BUSMOD <When reset: H'00> Bit Name Function 8-14 No functions assigned...
Page 732 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations 17.2 Read/Write Operations (1) When Bus Mode Control Register = 0 (WR signal separate mode) External read/write operations are performed using the address and data buses and the CS0, ___ ___ ___ __ ___ ___ ____ CS1, CS2, CS3, RD, BHW, BLW, WAIT, and BCLK signals.
Page 733 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations Read Read (2 cycles) 1 wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 – DB15 WAIT "H" Write Write (2 cycles) 1 wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H"...
Page 734 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations Read (4 cycles) Read 1 external 2 internal wait states wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 – DB15 WAIT "H" "L" (Don't Care) Write Write (4 cycles) 1 external 2 internal wait states wait state...
Page 735 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations (2) When Bus Mode Control Register = 1 (WR signal separate mode) External read/write operations are performed using the address and data buses and the CS0, ___ ___ ___ __ ___ ___ ____ CS1, CS2, CS3, RD, BHE, BLE, WAIT, and WR signals. In an external read cycle, the RD signal goes low and the BHE or BLE signal for the byte position to read goes low, so that the data at only the necessary byte position is read.
Page 736 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations Read Read (2 cycles) 1 wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 – DB15 WAIT "H" Write Write (2 cycles) 1 wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H"...
Page 737 EXTERNAL BUS INTERFACE 17.2 Read/Write Operations Read (4 cycles) Read 1 external 2 internal wait states wait state BCLK A12 – A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 – DB15 WAIT "H" (Don't Care) "L" Write Write (4 cycles) 1 external 2 internal wait states wait state...
Page 738 EXTERNAL BUS INTERFACE 17.3 Bus Arbitration 17.3 Bus Arbitration (1) When Bus Mode Control Register = 0 (WR signal separate mode) ____ When the input signal at the HREQ pin is asserted low and the hold request is accepted, the CPU ____ enters a hold state in which it outputs a low from the HACK pin.
Page 739 EXTERNAL BUS INTERFACE 17.3 Bus Arbitration (2) When Bus Mode Control Register = 1 (Byte enable separate mode) ____ When the input signal at the HREQ pin is asserted low and the hold request is accepted, the CPU ____ enters a hold state in which it outputs a low from the HACK pin. During hold, the bus related signals go to a high-impedance state, allowing data transfers to be performed on the system bus.
Page 740 EXTERNAL BUS INTERFACE 17.4 Example for Connecting External Extension Memory 17.4 Example for Connecting External Extension Memory (1) When Bus Mode Control Register = 0 (with two memory blocks connected) Figure 17.4.1 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode).
Page 741 (2) When Bus Mode Control Register = 0 (with three memory blocks connected) Figure 17.4.2 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Flash memory Memory mapping 32172,32173 H'0000 0000 Internal flash memory (256KB) A[13:30]...
Page 742 (3) When Bus Mode Control Register = 0 (with four memory blocks connected) Figure 17.4.3 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Flash memory Memory mapping 32172,32173 H'0000 0000 Internal flash memory (256KB) A[14:30]...
Page 743 EXTERNAL BUS INTERFACE 17.4 Example for Connecting External Extension Memory (4) When Bus Mode Control Register = 1 (with two memory blocks connected) Figure 17.4.4 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Memory mapping Flash memory M32172F2...
Page 744 EXTERNAL BUS INTERFACE 17.4 Example for Connecting External Extension Memory (5) When Bus Mode Control Register = 1 using 8/16-bit data bus memory blocks in combination Figure 17.4.3 shows a typical connection diagram for the microcomputer when using an 8-bit data bus memory which is located in the CS0 area and a 16-bit data bus memory which is located in the CS1 area.
Page 745: Chapter 18 Wait Controller
CHAPTER 18 CHAPTER 18 WAIT CONTROLLER 18.1 Outline of the Wait Controller 18.2 Wait Controller Related Registers 18.3 Typical Operation of the Wait Controller...
Page 746 WAIT CONTROLLER 18.1 Outline of the Wait Controller 18.1 Outline of the Wait Controller The Wait Controller controls the number of wait cycle inserted in the bus cycle when accessing an external extended area. The Wait Controller is outlined below. Table 18.1.1 Outline of the Wait Controller Item Specification...
Page 747 WAIT CONTROLLER 18.1 Outline of the Wait Controller Non-CS0 area H'0000 0000 Internal ROM area (256 Kbytes) H'0003 FFFF H'0004 0000 Reserved area (768 Kbytes) H'000F FFFF CS0 area H'0010 0000 (2 Mbytes) CS0 area (1 Mbytes) H'001F FFFF H'0020 0000 CS1 area CS1 area (2 Mbytes)
Page 748 WAIT CONTROLLER 18.1 Outline of the Wait Controller Table 18.1.2 Number of Wait Cycles That Can Be Set by the Wait Controller during External Extended Mode Valid chip External Address Number of wait cycles inserted select signal extended area CS0 , CS1 CS0 area H'0010 0000–H'001F FFFF One to four wait cycles inserted by setting in...
Page 749 WAIT CONTROLLER 18.1 Outline of the Wait Controller Table 18.1.3 Number of Wait Cycles That Can Be Set by the Wait Controller during Processor Mode External extended area Address Number of wait cycles inserted CS0 area H'0000 0000–H'000F FFFF One to four wait cycles inserted by setting in ____ (Note 1) software + any wait cycles inserted by WAIT pin...
Page 750 WAIT CONTROLLER 18.2 Wait Controller Related Registers 18.2 Wait Controller Related Registers A wait controller related register map is shown below. Address +0 address +1 address Wait Cycles Control Register H'0080 0180 (WTCCR) Blank areas are reserved for future use. Figure 18.2.1 Wait Controller Related Register Map 18-6 Rev.1.0...
Page 751: Wait States Control Register
WAIT CONTROLLER 18.2 Wait Controller Related Registers 18.2.1 Wait States Control Register Wait States Control Register (WTCCR) <Address: H'0080 0180> CS2WTC CS0WTC CS3WTC CS1WTC <When reset: H'00> Bit Name Function CS2WTC 00: 4 wait cycles (when reset) (Control the number of 01: 3 wait cycles CS2 wait states) 10: 2 wait cycles...
Page 752: Typical Operation Of The Wait Controller
WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller 18.3 Typical Operation of the Wait Controller The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller.
Page 753 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" Write Write (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 "H"...
Page 754 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 755 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1, CS0, CS1...
Page 756 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) Write Write (5 cycles) 4 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 757 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (6 cycles) 1 external 4 internal wait cycles wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) "L" Write Write (6 cycles) 1 external...
Page 758 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (3+n cycles) 2 internal wait cycles n external wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHW, BLW DB0 - DB15 WAIT "H" (Don't Care) "L" "L"...
Page 759 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller (2) When Bus Mode Control Register = 1 External read/write operations are performed using the address bus, data bus, and signals CS0, ____ CS1, CS2, CS3, RD, BHE, BLE, WAIT, and WR. Bus-free state internal bus access BCLK...
Page 760 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (2 cycles) 1 internal wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" Write Write (2 cycles) 1 internal wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 761 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write Write (3 cycles) 2 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 762 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read Read (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write Write (4 cycles) 3 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 763 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read (5 cycles) Read 4 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) Write (5 cycles) Write 4 internal wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3...
Page 764 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read (6 cycles) Read 1 external 4 internal wait cycles wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" Write (6 cycles) Write 1 external...
Page 765 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller Read (3+n cycles) Read 2 internal wait cycles n external wait cycles BCLK A12 - A30 CS0, CS1, CS2, CS3 "H" BHE, BLE DB0 - DB15 WAIT "H" (Don't Care) "L" "L"...
Page 766 WAIT CONTROLLER 18.3 Typical Operation of the Wait Controller * This is a blank page.* 18-22 Rev.1.0...
Page 767: Chapter 19 Ram Backup Mode
CHAPTER 19 CHAPTER 19 RAM BACKUP MODE 19.1 Outline 19.2 Example of RAM Backup when Power is Down 19.3 Example of RAM Backup for Saving Power Consumption 19.4 Exiting RAM Backup Mode (Wakeup)
Page 768: Outline
RAM BACKUP MODE 19.1 Outline 19.1 Outline In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes: • Back up the internal RAM data when the power is down •...
Page 769: Normal Operating State
RAM BACKUP MODE 19.2 Example of RAM Backup when Power is Down 19.2.1 Normal Operating State Figure 19.2.2 shows the normal operating state of the M32R/E. During normal operation, input on _______ the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. DC IN Input Output...
Page 770: Ram Backup State
RAM BACKUP MODE 19.2 Example of RAM Backup when Power is Down 19.2.2 RAM Backup State Shown in Figure 19.2.3 is the power outage RAM backup state of the M32R/E. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/E.
Page 771: Example Of Ram Backup For Saving Power Consumption
RAM BACKUP MODE 19.3 Example of RAM Backup for Saving Power Consumption 19.3 Example of RAM Backup for Saving Power Consumption Figure 19.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example.
Page 772: Normal Operating State
RAM BACKUP MODE 19.3 Example of RAM Backup for Saving Power Consumption 19.3.1 Normal Operating State Figure 19.3.2 shows the normal operating state of the M32R/E. During normal operation, the RAM backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high.
Page 773: Ram Backup State
RAM BACKUP MODE 19.3 Example of RAM Backup for Saving Power Consumption 19.3.2 RAM Backup State Figure 19.3.3 shows the RAM backup state of the M32R/E. Figure 19.3.4 shows a RAM backup sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and in Figure 19.3.3).
Page 774: Precautions To Be Observed At Power-On
RAM BACKUP MODE 19.3 Example of RAM Backup for Saving Power Consumption Power on RAM backup period 5.0V VCCE, VREFn, AVCCn 3.3V VCCI, OSC-VCC Port output setting Port output setting Port input mode (High level) (High level) Port X External input External input signal goes high signal goes low...
Page 775: Exiting Ram Backup Mode (Wakeup)
RAM BACKUP MODE 19.4 Exiting RAM Backup Mode (Wakeup) 19.4 Exiting RAM Backup Mode (Wakeup) Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 19.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input.
Page 776 RAM BACKUP MODE 19.4 Exiting RAM Backup Mode (Wakeup) * This is a blank page.* 19-10 Rev.1.0...
Page 777: Chapter 20 Oscillation Circuit
CHAPTER 20 CHAPTER 20 OSCILLATION CIRCUIT 20.1 Oscillator Circuit 20.2 Clock Generator Circuit...
Page 778: Oscillator Circuit
OSCILLATION CIRCUIT 20.1 Oscillator Circuit 20.1 Oscillator Circuit The M32R/E contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory.
Page 779: System Clock Output Function
OSCILLATION CIRCUIT 20.1 Oscillator Circuit 20.1.2 System Clock Output Function A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1.
Page 780: Oscillation Stabilization Time At Power-On
OSCILLATION CIRCUIT 20.1 Oscillator Circuit 20.1.3 Oscillation Stabilization Time at Power-on The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used.
Page 781: Clock Generator Circuit
OSCILLATION CIRCUIT 20.2 Clock Generator Circuit 20.2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits. CPU clock (32MHz - 40MHz) (8MHz - 10MHz) BCLK (16MHz - 20MHz) 1/2 internal peripheral clock (8MHz - 10MHz) Figure 20.2.1 Configuration of the Clock Generator Circuit 20-5 Rev.1.0...
Page 782 OSCILLATION CIRCUIT 20.2 Clock Generator Circuit * This is a blank page.* 20-6 Rev.1.0...
Page 783: Chapter 21 Jtag
CHAPTER 21 CHAPTER 21 JTAG 21.1 Outline of the JTAG 21.2 Configuration of the JTAG Circuit 21.3 JTAG Registers 21.4 Basic Operation of the JTAG 21.5 Boundary Scan Description Language 21.6 Precautions on Board Design when Connecting the JTAG 21.7 Processing Pins when Not Using the JTAG...
Page 784 21.1 Outline of the JTAG 21.1 Outline of the JTAG The 32172/32173 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std.
Page 785 21.2 Configuration of the JTAG Circuit 21.2 Configuration of the JTAG Circuit The 32172/32173's JTAG circuit consists of the following blocks: • Instruction register to hold instruction codes which are fetched through the boundary-scan path • A set of data registers which are accessed through the boundary-scan path •...
Page 786: Instruction Register (Jtagir)
[Capture-IR] → [Exit1-IR] → [Update-IR] The 32172/32173's JTAG interface supports the following instructions: • Three instructions stipulated as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS) •...
Page 787: Data Registers
(2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32172/ 32173 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction.
Page 788: Basic Operation Of The Jtag
JTAG 21.4 Basic Operation of the JTAG 21.4 Basic Operation of the JTAG 21.4.1 Outline of JTAG Operation The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state.
Page 789 JTAG 21.4 Basic Operation of the JTAG The state transitions of the TAP controller and the basic configuration of the 32171's JTAG related registers are shown below. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR...
Page 790 JTAG 21.4 Basic Operation of the JTAG 21.4.2 IR Path Sequence Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below.
Page 791 JTAG 21.4 Basic Operation of the JTAG JTDI input is sampled at rise Instruction code is set in the parallel output of JTCK in "Shift-IR" state. stage at fall of JTCK in "Update-IR" state. JTCK JTMS state JTDI Don't Care Don't Care Instruction code (6 bits) LSB value...
Page 792 JTAG 21.4 Basic Operation of the JTAG 21.4.3 DR Path Sequence The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below.
Page 793 JTAG 21.4 Basic Operation of the JTAG JTDI input is sampled at rise Setup data is set in the parallel output stage of JTCK in "Shift-DR" state. at fall of JTCK in "Update-DR" state. JTCK JTMS state JTDI Don't Care Don't Care LSB value MSB value...
Page 794: Examining And Setting Data Registers
JTAG 21.4 Basic Operation of the JTAG 21.4.4 Examining and Setting Data Registers To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit).
Page 795 JTAG 21.4 Basic Operation of the JTAG Test-Logic- Run-Test IR path DR path Run-Test IR path DR path Reset state /Idle state sequence sequence /Idle state sequence sequence states JTDI Instruction Setup data Instruction Setup data (Note 1) code code Fixed Fixed JTDO...
Page 796: Boundary Scan Description Language
The BSDL for the 32172/32173 shown in the pages to follow have been prepared for use in test engineering for the purpose of PCB design and those stipulated in IEEE 1149.1 standards.
Page 797 -- Boundary Scan Description Language (BSDL) for -- M32173F2VFP: M32R/E M32173 Group, Flash 256KB, 144P6Q -------------------------------------------------------------------- -- Modification History -- Date Author Version -- Created '00/10/05 MITSUBISHI Ver. 0.0 -- Modified '--/--/-- -------------------------------------------------------------------- entity M32173F2VFP is generic (PHYSICAL_PIN_MAP : string := "P6Q144"); port ( P221 bit;...
Page 798 JTAG 21.5 Boundary Scan Description Language AD0IN2 :linkage bit; AD0IN3 :linkage bit; AD0IN4 :linkage bit; AD0IN5 :linkage bit; AD0IN6 :linkage bit; AD0IN7 :linkage bit; AD1IN0 :linkage bit; AD1IN1 :linkage bit; AD1IN2 :linkage bit; AD1IN3 :linkage bit; :linkage bit; :linkage bit; P172 bit;...
Page 799 JTAG 21.5 Boundary Scan Description Language P101 :inout bit; P102 :inout bit; VDD_108 :linkage bit; bit; bit; TRST bit; :out bit; bit; P103 :inout bit; P104 :inout bit; P105 :inout bit; P106 :inout bit; P107 :inout bit; P124 bit; P125 bit;...
Page 800 JTAG 21.5 Boundary Scan Description Language "P35 :13," & "P36 :14," & "P37 :15," & "P20 :16," & "P21 :17," & "P22 :18," & "P23 :19," & "VCCE_20 :20," & "VSS_21 :21," & "P24 :22," & "P25 :23," & "P26 :24,"...
Page 801 JTAG 21.5 Boundary Scan Description Language "FVCC_73 :73," & "P61 :74," & "P62 :75," & "P63 :76," & "P64 :77," & "P70 :78," & "P71 :79," & "P72 :80," & "P73 :81," & "P74 :82," & "P75 :83," & "P76 :84,"...
Page 802 JTAG 21.5 Boundary Scan Description Language "P150 :133," & "P153 :134," & "P41 :135," & "P42 :136," & "VCCI_137 :137," & "VSS_138 :138," & "P43 :139," & "P44 :140," & "P45 :141," & "P46 :142," & "P47 :143," & "P220 :144"...
Page 803 JTAG 21.5 Boundary Scan Description Language attribute IDCODE_REGISTER of M32173F2VFP : entity is "0000" & -- version "0011001000100001" & -- part number "00000011100" & -- manufacturer's identity "1"; -- required by 1149.1 attribute USERCODE_REGISTER of M32173F2VFP : entity is "0000 0000 0000 0000" & -- reserved "0000"...
Page 804 JTAG 21.5 Boundary Scan Description Language "242 (BC_4, P133, observe_only, X)," & "241 (BC_4, P134, observe_only, X)," & "240 (BC_4, P135, observe_only, X)," & "239 (BC_4, P136, observe_only, X)," & "238 (BC_4, P137, observe_only, X)," & "237 (BC_4, P150, observe_only, X)," & "236 (BC_1, P150, output3,...
Page 805 JTAG 21.5 Boundary Scan Description Language "182 (BC_4, P37, observe_only, X)," & "181 (BC_1, P37, output3, X, 180, 0, Z)," & "180 (BC_1, control, 0)," & "179 (BC_4, P20, observe_only, X)," & "178 (BC_1, P20, output3, X, 177, 0, Z)," & "177 (BC_1, control, 0),"...
Page 806 JTAG 21.5 Boundary Scan Description Language "122 (BC_4, P13, observe_only, X)," & "121 (BC_1, P13, output3, X, 120, 0, Z)," & "120 (BC_1, control, 0)," & "119 (BC_4, P14, observe_only, X)," & "118 (BC_1, P14, output3, X, 117, 0, Z)," & "117 (BC_1, control, 0),"...
Page 807 JTAG 21.5 Boundary Scan Description Language "62 (BC_4, P73, observe_only, X)," & "61 (BC_1, P73, output3, X, 60, 0, Z)," & "60 (BC_1, control, 0)," & "59 (BC_4, P74, observe_only, X)," & "58 (BC_1, P74, output3, X, 57, 0, Z)," & "57 (BC_1, control, 0),"...
Page 808 :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; :inout bit; VREF_42 :linkage bit; AVCC_43 :linkage bit; AD0IN0 :linkage bit; AD0IN1 :linkage bit; Figure 21.5.12 BSDL Description for the 32172(1/11) 21-26 Rev.1.0...
Page 809 VSS_96 :linkage bit; P110 :inout bit; P111 :inout bit; P112 :inout bit; P113 :inout bit; P114 :inout bit; P115 :inout bit; P116 :inout bit; P117 :inout bit; P100 :inout bit; Figure 21.5.13 BSDL Description for the 32172(2/11) 21-27 Rev.1.0...
Page 810 :2," & "OSCVSS_3 :3," & "XIN :4," & "XOUT :5," & "OSCVCC_6 :6," & "VCNT_7 :7," & "P30 :8," & "P31 :9," & "P32 :10," & "P33 :11," & "P34 :12," & Figure 21.5.14 BSDL Description for the 32172(3/11) 21-28 Rev.1.0...
Page 811 :62," & "P174 :63," & "P175 :64," & "VCCE_65 :65," & "P82 :66," & "P83 :67," & "P84 :68," & "P85 :69," & "P86 :70," & "P87 :71," & "VSS_72 :72," & Figure 21.5.15 BSDL Description for the 32172(4/11) 21-29 Rev.1.0...
Page 812 :122," & "VCCI_123 :123," & "P130 :124," & "P131 :125," & "P132 :126," & "P133 :127," & "P134 :128," & "P135 :129," & "P136 :130," & "P137 :131," & "VCCE_132 :132," & Figure 21.5.16 BSDL Description for the 32172(5/11) 21-30 Rev.1.0...
Page 813 INSTRUCTION_PRIVATE of M32172F2VFP : entity is "MDM_SYSTEM," & "MDM_CONTROL," & "MDM_SETUP," & "MTM_CONTROL," & "MON_CODE," & "MON_DATA," & "MON_PARAM," & "MON_ACCESS," & "DMA_RADDR," & "DMA_RDATA," & "DMA_RTYPE," & "DMA_ACCESS," & "RTDENB" ; Figure 21.5.17 BSDL Description for the 32172(6/11) 21-31 Rev.1.0...
Page 814 X)," & "247 (BC_4, P126, observe_only, X)," & "246 (BC_4, P127, observe_only, X)," & "245 (BC_4, P130, observe_only, X)," & "244 (BC_4, P131, observe_only, X)," & "243 (BC_4, P132, observe_only, X)," & Figure 21.5.18 BSDL Description for the 32172(7/11) 21-32 Rev.1.0...
Page 815 X, 186, 0, Z)," & "186 (BC_1, control, 0)," & "185 (BC_4, P36, observe_only, X)," & "184 (BC_1, P36, output3, X, 183, 0, Z)," & "183 (BC_1, control, 0)," & Figure 21.5.19 BSDL Description for the 32172(8/11) 21-33 Rev.1.0...
Page 816 X, 126, 0, Z)," & "126 (BC_1, control, 0)," & "125 (BC_4, P12, observe_only, X)," & "124 (BC_1, P12, output3, X, 123, 0, Z)," & "123 (BC_1, control, 0)," & Figure 21.5.20 BSDL Description for the 32172(9/11) 21-34 Rev.1.0...
Page 817 X, 66, 0, Z)," & "66 (BC_1, control, 0)," & "65 (BC_4, P72, observe_only, X)," & "64 (BC_1, P72, output3, X, 63, 0, Z)," & "63 (BC_1, control, 0)," & Figure 21.5.21 BSDL Description for the 32172(10/11) 21-35 Rev.1.0...
Page 818 X, 3, 0, Z)," & "3 (BC_1, control, 0)," & "2 (BC_4, P102, observe_only, X)," & "1 (BC_1, P102, output3, X, 0, 0, Z)," & "0 (BC_1, control, 0)"; end M32172F2VFP; Figure 21.5.22 BSDL Description for the 32172(11/11) 21-36 Rev.1.0...
Page 819: Precautions On Board Design When Connecting The Jtag
JTAG 21.6 Precautions on Board Design when Connecting the JTAG 21.6 Precautions on Board Design when Connecting the JTAG The JTAG pins must have their wiring lengths matched during board design. This is necessary to accomplish fast, highly reliable communication with the JTAG tool. JTAG tool SDI connector (JTAG connector) VCCE(5V)
Page 820 JTAG 21.6 Precautions on Board Design when Connecting the JTAG SDI connector (JTAG connector) When connecting VCCE(5V) the JTAG tool Power M32R/E 10KΩ 33Ω JTDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω TRST JTRST 2KΩ 10KΩ 33Ω 33Ω...
Page 821: Processing Pins When Not Using The Jtag
JTAG 21.7 Processing Pins when Not Using the JTAG 21.7 Processing Pins when Not Using the JTAG When not using the JTAG, make sure the pins on the microcomputer are processed properly, as shown below. VCCE(5V) M32R/E 0 to 100K‰ JTDO 0 to 10K‰...
Page 822 JTAG 21.7 Processing Pins when Not Using the JTAG VCCE(5V) M32R/E 0 to 100K‰ JTDO 0 to 100K‰ JTDI 0 to 100K‰ JTMS 0 to 100K‰ JTCK JTRST 0 to 100K‰ 0 to 100K‰ TRCLK ( OPEN ) TRSYNC ( OPEN ) TRDATA[0:7] ( OPEN ) ( OPEN )
Page 823: Configuration Of The Power Supply Circuit
CHAPTER 22 CHAPTER 22 POWER-UP/POWER- SHUTDOWN SEQUENCE 22.1 Configuration of the Power Supply Circuit 22.2 Power-On Sequence 22.3 Power-Shutdown Sequence...
Page 824 POWER-UP/POWER-SHUTDOWN SEQUENCE 22.1 Configuration of the Power Supply Circuit 22.1 Configuration of the Power Supply Circuit To materialize high-speed operation at low power, the M32R/E is designed in such a way that its external interface circuits operate at 5 V power supply and all other circuits operate at 3.3 V. This requires that control timing of both 5 V and 3.3 V power supplies be considered when designing your circuit.
Page 825: Power-On Sequence When Not Using Ram Backup
POWER-UP/POWER-SHUTDOWN SEQUENCE 22.2 Power-On Sequence 22.2 Power-On Sequence 22.2.1 Power-On Sequence When Not Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when not using RAM backup. VCCE AVCC0 VREF0 RESET 3.3V 3.3V...
Page 826: Power-On Sequence When Using Ram Backup
POWER-UP/POWER-SHUTDOWN SEQUENCE 22.2 Power-On Sequence 22.2.2 Power-On Sequence When Using RAM Backup The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when using RAM backup. VCCE AVCC0 VREF0 RESET 3.3V 2.0V 3.3V VCCI 3.3V FVCC 3.3V...
Page 827: Power-Shutdown Sequence
POWER-UP/POWER-SHUTDOWN SEQUENCE 22.3 Power-Shutdown Sequence 22.3 Power-Shutdown Sequence 22.3.1 Power-Shutdown Sequence When Not Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when not using RAM backup. VCCE AVCC0 VREF0 RESET 3.3V...
Page 828: Power-Shutdown Sequence When Using Ram Backup
POWER-UP/POWER-SHUTDOWN SEQUENCE 22.3 Power-Shutdown Sequence 22.3.2 Power-Shutdown Sequence When Using RAM Backup The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when using RAM backup. VCCE AVCC0 VREF0 P72 / HREQ RESET 3.3V 2.0V 3.3V...
Page 829 POWER-UP/POWER-SHUTDOWN SEQUENCE 22.3 Power-Shutdown Sequence M32R/E VCCE 5V power supply I/O control circuit AVCC0 A-D converter circuit VCCI 3.3V 3.3V power supply Peripheral circuits FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 22.3.3 Microcomputer Ready to Run State (VCCE = 5 V, VCCI system = 3.3 V, VDD = 3.3 V) M32R/E VCCE I/O control circuit...
Page 830 POWER-UP/POWER-SHUTDOWN SEQUENCE 22.3 Power-Shutdown Sequence M32R/E VCCE I/O control circuit 5V power supply AVCC0 A-D converter circuit VCCI 3.3V power supply Peripheral circuits FVCC Flash OSC-VCC Oscillator and PLL circuits Figure 22.3.5 CPU Halt State M32R/E VCCE 5V power supply I/O control circuit AVCC0 A-D converter circuit...
Page 831: Absolute Maximum Ratings
CHAPTER 23 CHAPTER 23 ELECTRICAL CHARACTERISTICS 23.1 Absolute Maximum Ratings 23.2 Recommended Operating Conditions 23.3 DC Characteristics 23.4 A-D Conversion Characteristics 23.5 D-A Conversion Characteristics 23.6 AC Characteristics...
Page 832 TOPR -40 — 125 Temperature (Note) -65 — 150 Tstg Storage Temperature Note: This does not guarantee that the device will operate continuously at 125°C. If your application system is intended to operate at 125°C, please consult Mitsubishi. 23-2 Rev.1.0...
Page 833 ELECTRICAL CHARACTERISTICS 23.2 Recommended Operating Conditions 23.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 85°C unless otherwise specified) Symbol Parameter Rated Value Unit VCCE External I/O Buffer Voltage (Note 1) VCCI Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2)
Page 834 ELECTRICAL CHARACTERISTICS 23.2 Recommended Operating Conditions Recommended Operating Conditions (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 125°C unless otherwise specified) Symbol Parameter Rated Value Unit VCCE External I/O Buffer Voltage (Note 1) VCCI Internal Logic Power Supply Voltage (Note 2) RAM Power Supply Voltage (Note 2)
Page 835 ELECTRICAL CHARACTERISTICS 23.3 DC Characteristics 23.3 DC Characteristics 23.3.1 Electrical Characteristics (1) Electrical Characteristics when f(XIN) = 10 MHz (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 85°C unless otherwise specified) Symbol Parameter Test Condition Rated Value...
Page 836 ELECTRICAL CHARACTERISTICS 23.3 DC Characteristics (2) Electrical Characteristics of Each Power Supply Pin when f(XIN) = 10 MHz (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 85°C unless otherwise specified) Symbol Parameter Test Condition Rated Value Unit...
Page 837 ELECTRICAL CHARACTERISTICS 23.3 DC Characteristics (4) Electrical Characteristics when f(XIN) = 8 MHz (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 125°C unless otherwise specified) Symbol Parameter Test Condition Rated Value Unit High Level Output Voltage VCCE + 0.165 -2mA...
Page 838 ELECTRICAL CHARACTERISTICS 23.3 DC Characteristics (5) Electrical Characteristics of Each Power Supply Pin when f(XIN) = 8 MHz (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 125°C unless otherwise specified) Test Condition Symbol Parameter Rated Value...
Page 839: Flash Related Electrical Characteristics
ELECTRICAL CHARACTERISTICS 23.3 DC Characteristics 23.3.2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V unless otherwise specified) Symbol Parameter Test Condition Rated Value Unit FVCC Power Supply Current fvcc (when Programming) FVCC Power Supply Current...
Page 840: A-D Conversion Characteristics
ELECTRICAL CHARACTERISTICS 23.4 DC Characteristics 23.4 A-D Conversion Characteristics A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz unless otherwise specified) Symbol Parameter Test Condition Rated Value Unit Resolution Bits...
Page 841: D-A Conversion Characteristics
ELECTRICAL CHARACTERISTICS 23.5 D-A Conversion Characteristics 23.5 D-A Conversion Characteristics 23.5.1 D-A Conversion Characteristics D-A Conversion Characteristics (Referenced to AVCC = VREF = VCCF = 5.12 V, Ta = 25°C, f(XIN) = 10/8 MHz unless otherwise specified) Symbol Parameter Test Condition Rated Value Unit Resolution...
Page 842: Ac Characteristics
ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics 23.6 AC Characteristics 23.6.1 Timing Requirements • Unless otherwise noted, timing conditions are VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C • The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF (however, 80 pF for JTAG-related).
Page 843 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics (4) TINi (i=0, 3, 16-23) Symbol Parameter Condition Unit Rated Value Figure 23.6.5 TINi Input Pulse Width tc(BCLK) w(TINi) (5) TIN8-11 (When multiply-by-4 event count or up/down event count mode) Parameter Condition Rated Value Symbol Figure Unit 23.6.6...
Page 844 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics (7) Bus arbitration timing Symbol Parameter Condition Unit Rated Value Figure 23.6.10 HREQ Input Setup Time before BCLK su(HREQL-BCLKH) HREQ Input Hold Time after BCLK h(BCLKH-HREQL) (8) Input transition time on JTAG pin Rated Value Figure Symbol Condition...
Page 845 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics (10) RTD Timing Rated Value Parameter Symbol Figure Unit 23.6.13 tc(RTDCLK) RTDCLK Input Cycle Time tw(RTDCLKH) RTDCLK Input High Pulse Width tw(RTDCLKL) RTDCLK Input Low Pulse Width RTDACK Delay Time after RTDCLK Input td(RTDCLKH-RTDACK) tv(RTDCLKL-RTDACK) RTDACK Valid Time after RTDCLK Input td(RTDCLKH-RTDTXD) RTDTXD Delay Time after RTDCLK Input...
Page 846: Switching Characteristics
ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics 23.6.2 Switching Characteristics (1) Input/output ports Rated Value Symbol Parameter Condition Unit Figure 23.6.1 Port Data Output Delay Time d(E-P) (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Unit Parameter Condition Rated Value Figure 23.6.2 TxD Output Delay Time...
Page 847 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics (4) Read and write timing Rated Value Figure Symbol Parameter Condition Unit 23.6.7 23.6.8 23.6.9 tc(Xin) BCLK Output Cycle Time c(BCLK) tc(BCLK) BCLK Output High Pulse Width w(BCLKH) tc(BCLK) BCLK Output Low Pulse Width w(BCLKL) Address Delay Time after BCLK d(BCLKH-A) Chip Select Delay Time after BCLK...
Page 848 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics Read and write timing (continued from the preceding page) Symbol Parameter Condition Unit Rated Value Figure 23.6.7 23.6.8 23.6.9 Data Output Delay Time after Write d(BLWL-D) d(BHWL-D) (Byte write mode) Valid Data Output Time after Write tc(BCLK) v(BLWH-D) (Byte write mode)
Page 849 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics 23.6.3 AC Characteristics 0.8VCCE BCLK 0.2VCCE tsu(P-E) th(E-P) 0.8VCCE 0.8VCCE Port input 0.2VCCE 0.2VCCE td(E-P) 0.8VCCE Port output 0.2VCCE Figure 23.6.1 Input/Output Port Timing a) CSIO mode, with internal clock selected 0.8VCCE 0.2VCCE th(CLK-D) td(CLK-D) 0.8VCCE 0.2VCCE th(CLK-D)
Page 850 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics 0.2VCCE 0.2VCCE tw(SBIL) Figure 23.6.3 SBI Timing BCLK 0.2VCCE td(BCLK-TOi) 0.8VCCE 0.2VCCE Figure 23.6.4 TOi Timing tw(TINi) 0.8VCCE 0.8VCCE TINi 0.2VCCE 0.2VCCE Figure 23.6.5 TINi Timing tw(TINi) 0.8VCCE 0.8VCCE TIN8-11 0.2VCCE 0.2VCCE 0.8Vcc 0.8Vcc 0.2Vcc 0.2Vcc TIN8(10) TIN9(11)
Page 851 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics tw(BCLKL) tc(BCLK) tw(BCLKH) BCLK 0.43VCCE 0.16VCCE tv(BCLKH-CS) td(BCLKH-CS) tv(BCLKH-A) td(BCLKH-A) td(BCLKL-RDL) Address 0.43VCCE 0.43VCCE (A12-A30) 0.16VCCE 0.16VCCE CS0 , CS1 tv(RDH-A) td(CS-RDL) tv(RDH-CS) td(A-RDL) tw(RDL) 0.43VCCE 0.43VCCE 0.16VCCE 0.16VCCE tw(RDH) tv(BCLKH-RDL) th(RDH-D) tsu(D-RDH) Data Input 0.43VCCE 0.43VCCE (D0-D15)
Page 852 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics tw(BCLKL) tc(BCLK) tw(BCLKH) 0.43VCCE BCLK 0.16VCCE 0.16VCCE tv(BCLKH-CS) td(BCLKH-CS) tv(BCLKH-A) td(BCLKH-A) Address 0.43VCCE 0.43VCCE (A12-A30) 0.16VCCE 0.16VCCE CS0 , CS1 td(RDH-BLWL) td(BCLKL-RDL) td(RDH-BHWL) 0.43VCCE 0.16VCCE tv(BCLKL-BLWL) tv(BCLKL-BHWL) td(CS-BLWL) td(CS-BHWL) td(BLWH-RDL) td(A-BLWL) tw(BLWL) td(BHWH-RDL) td(A-BHWL) tw(BHWL) 0.43VCCE 0.16VCCE tv(BLWH-CS)
Page 853 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics Address (A12-A30) 0.43VCCE 0.43VCCE 0.16VCCE 0.16VCCE CS0, CS1 td(RDH-BLEL) td(BLEH-RDL) td(RDH-BHEL) td(BHEH-RDL) 0.43VCCE 0.16VCCE td(CS-WRL) tv(WRH-CS) td(A-WRL) tv(WRH-A) tw(WRL) 0.43VCCE 0.16VCCE 0.16VCCE td(BLEL-WRL) tv(WRH-BLEL) tv(WRH-BHEL) td(BHEL-WRL) 0.43VCCE BLE , BHE 0.16VCCE 0.16VCCE tpxz(WRH-DZ) td(WRL-D) tv(WRH-D) Data output 0.43VCCE (D0-D15)
Page 854 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics JTCK,JTDI 0.8VCCE 0.8VCCE JTMS,JRST 0.2VCCE 0.2VCCE Note: Stipulated values are guaranteed values when the test pin load capacitance CL = 80 pF. Figure 23.6.11 Input Transition Time on JTAG pins tc(JTCK) tw(JTCKL) tw(JTCKH) 0.5VCCE JTCK th(JTCK-JTDI) tsu(JTDI-JTCK) Data input,...
Page 855 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics tc(RTDCLK) tw(RTDCLKH) tw(RTDCLKL) 0.5VCCE 0.5VCCE 0.5VCCE RTDCLK td(RTDCLKH-RTDACK) tv(RTDCLKH-RTDACK) 0.8VCCE RTDACK 0.2VCCE td(RTDCLKH-RTDTXD) 0.8VCCE RTDTXD 0.2VCCE tsu(RTDRXD-RTDCLKL) th(RTDCLKH-RTDACK) 0.8VCCE 0.8VCCE RTDRXD 0.2VCCE 0.2VCCE Figure 23.6.13 RTD Timing 23-25 Rev.1.0...
Page 856 ELECTRICAL CHARACTERISTICS 23.6 AC Characteristics *** This is a blank page *** 23-26 Rev.1.0...
Page 857: Chapter 24 Standard Characteristics
CHAPTER 24 CHAPTER 24 STANDARD CHARACTERISTICS 24.1 A-D Conversion Characteristics...
Page 858 STANDARD CHARACTERISTICS 24.1 A-D Conversion Characteristics 24.1 A-D Conversion Characteristics To be written at a later time 24-2 Rev.1.0...
Page 859: Specifications
APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing...
Page 860 MECHANICAL SPECIFICATIONS Appendix 1 Appendix 1.1 Dimensional Outline Drawing Appendix 1.1 Dimensional Outline Drawing (1) 144 pin LQFP Appendix 1-2 Rev.1.0...
Page 861 APPENDIX 2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/E Instruction Processing Time...
Page 862 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 M32R/E Instruction Processing Time Appendix 2.1 M32R/E Instruction Processing Time For the M32R, the number of instruction execution cycles in E stage normally represents its instruction processing time. However, depending on pipeline operation, other stages may affect the instruction processing time.
Page 863 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 M32R/E Instruction Processing Time The following shows the number of memory access cycles in IF and MEM stages. Shown here are the minimum number of cycles required for memory access. Therefore, these values do not always reflect the number of cycles required for actual memory or bus access.
Page 864 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 M32R/E Instruction Processing Time This is a blank page. Appendix 2-4 Rev.1.0...
Page 865 APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3.1 Precautions about Noise...
Page 866 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system with these measures incorporated be fully evaluated before it can actually be put to use.
Page 867 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise (2) Wiring of clock input/output pins Reduce the length of wiring connecting to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its ground lead wire and the VSS pin on the microcomputer are connected with the shortest possible wiring (within 20 mm).
Page 868 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 mF between VSS and VCC lines in such a way as to meet the requirements described below.
Page 869 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.3 Processing Analog Input Pin Wiring Connect a resistor of about 100 to 500 W ( in series to the analog signal wire connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible.
Page 870 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.4 Consideration about the Oscillator The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it less susceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator) as possible.
Page 871 INSTRUCTION PROCESSING TIME Appendix 3 Appendix 3.1 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure rapidly level-changing signal lines will not intersect clock-related signal lines and other noise-sensitive signal lines.
Page 872 PRECAUTIONS ABOUT NOISE Appendix 3 Appendix 3.1 Precautions about Noise Appendix 3.1.5 Processing Input/Output Ports For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100 W (or more) in series to input/output ports. Software measures •...
Page 873 USER’S MANUAL 32172/32173 Group Oct. First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor User’s Manual Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
Page 874 User’s Manual 32172/32173 Group HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN New publication, effective Jul. 2001. © 2001 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.

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32173

Mitsubishi 32172 User Manual

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Address Space

Chapter 4 Eit

Chapter 5 Interrupt Controller (Icu)

Chapter 6 Internal Memory

Chapter 7 Reset

Chapter 8 Input/Output Ports and Pin Functions

Chapter 9 Dmac

Chapter 10 Input/Output Timers

Chapter 11 A-D Converters

Chapter 12 Serial I/O

Chapter 13 Can Modules

Chapter 14 Real-Time Debugger (Rtd)

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