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Pin
Port Name
No.
48 RXD1/SCL1/STXD1/P6_6
49 P11_7
50 CLK1/P6_5
N_CTS1/N_RTS1/N_SS1/OUTC2_1/
51
ISCLK2/P6_4
52 TXD0/SDA0/SRXD0/P6_3
53 TB2IN/RXD0/SCL0/STXD0/P6_2
54 TB1IN/CLK0/P6_1
55 TB0IN/N_CTS0/N_RTS0/N_SS0/P6_0
56 P19_5
57 D31/OUTC2_7/P13_7
58 D30/OUTC2_1/ISCLK2/P13_6
59 D29/OUTC2_2/ISRXD2/IEIN/P13_5
60 D28/OUTC2_0/ISTXD2/IEOUT/P13_4
61 P19_4
62 RDY/CS3/N_CTS7/N_RTS7/P5_7
63 ALE/CS2/RXD7/P5_6
64 HOLD/CLK7/P5_5
65 HLDA/CS1/TXD7/P5_4
66 D27/OUTC2_3/P13_3
67 VSS
68 D26/OUTC2_6/P13_2
69 VCC
70 D25/OUTC2_5/P13_1
71 D24/OUTC2_4/P13_0
72 CLKOUT/BCLK/P5_3
73 RD/P5_2
74 WR1/BC1/P5_1
75 WR0/WR/P5_0
76 D23/P12_7
77 D22/P12_6
78 D21/P12_5
79 P19_3
80 P17_3
81 P17_2
82 P17_1
83 P17_0
84 P19_2
85 CS0/A23/TXD6/SDA6/SRXD6/P4_7
86 CS1/A22/RXD6/SCL6/STXD6/P4_6
87 CS2/A21/CLK6/P4_5
CS3/A20/N_CTS6/N_RTS6/N_SS6/
88
P4_4
A19/TXD3/SDA3/SRXD3/OUTC2_0/
89
ISTXD2/IEOUT/P4_3
90 P11_6
A18/RXD3/SCL3/STXD3/ISRXD2/IEIN/
91
P4_2
92 P11_5
93 A17/CLK3/P4_1
94 A16/N_CTS3/N_RTS3/N_SS3/P4_0
95 P16_7/TXD10
96 P16_6/RXD10
97 P16_5/CLK10
98 P16_4/N_CTS10/N_RTS10
99 A15/[A15/D15]/TA4IN/U/P3_7
100 A14/[A14/D14]/TA4OUT/U/P3_6
I/O
Function Name
Related Power Supply
232C_DBG_MISO
AC
---
AC
DBG_SCK
AC
DBG_BUSY
AC
DSP_MOSI
DSP_PON
DSP_MISO
DSP_PON
DSP_SCK
DSP_PON
NCPU_SPI_RDY
NCPU_PON
---
AC
DSP1_N_RST
DSP_PON
---
---
---
EEP_N_CS
AC
FPGA_N_CS
HDMI_PON
DFF2_N_CS
AC
DBG_EPM
AC
DFF1_N_CS
AC
---
AC
VSS
DSP1_N_SPIRDY
DSP_PON
VCC
---
AC
DSP1_N_CS
DSP_PON
NC(BCLK)
AC
MCBUS_N_RD
AC
NC(BC1)
AC
MCBUS_N_WR
HDMI_PON
DBG_N_CE
AC
MT_DA
DSP_PON
DIR1_N_CS
DSP_PON
DIR_N_RST
DSP_PON
---
AC
DIR1_N_INT
DSP_PON
---
AC
NCPU_PON
NCPU_PON
NCPU_VBUSDRV
NCPU_PON
USB_VBUS_PON
NCPU_PON
FLASH_N_CS
AC
A[22]
AC
A[21]
AC
A[20]
AC
A[19]
AC
HTX2_AUSEL
DSP_PON
A[18]
AC
DFF_FROM_N_RST AC
A[17]
AC
A[16]
AC
EX_MOSI
AC
EEP_MISO
AC
EX_SCK
AC
NCPU_AMUTE
NCPU_PON
A[15]
AC
A[14]
AC
RX-V675/HTR-6066/RX-A730/TSR-6750
Detail of Function
OFF
ON
O
I
RS-232C reception data / Debug / E8a
O
O
No used
O
I
E8a
O
O
E8a
O
O
DSP/DIR/DAC transmission data
I
I
DSP/DIR/DAC reception data
O
O
DSP/DIR/DAC communication clock
O
I
BridgeCO data ready
O
O
No used
O
O
DSP1 reset
Serial spare
Serial spare
Serial spare
O
O
EEPROM chip select
O
B
External bus FPGA chip select
O
B
External bus DFF2 chip select
I
I
E8a
O
B
External bus DFF1 chip select
O
O
No used
---
O
I
DSP1 SPI ready
---
O
O
No used
O
O
DSP1 chip select
O
B
External bus
O
B
External bus
O
B
External bus
I
B
External bus
I
I
E8a
O
O
Mute digital audio
O
O
DIR1 chip select
O
O
DIR reset
O
O
No used
O
I
Interrupt from DIR1 (for DAU_N_INT distinction)
O
O
No used
O
O
NET / USB power supply
O
I
USB VBUS drive
O
O
USB VBUS power supply control
O
O
External bus flash ROM chip select
O
B
External bus
O
B
External bus
O
B
External bus
O
B
External bus
O
O
HDMI TX2 sound select (main/zone ADC)
O
B
External bus
O
O
Reset of DFF and external ROM
O
B
External bus
O
B
External bus
O
O
FL/EEPROM transmission data
O
I
EEPROM reception data
O
O
FL/EEPROM communication clock
O
I
Mute signal from BridgeCO
O
B
External bus
O
B
External bus
89
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