Yamaha RX-V675 Service Manual page 75

Pin
Function Name
No.
1 AXR1[0]/GP4[0]
2 UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/
BOOT[8]
3 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/
BOOT[9]
4 AXR1[10]/GP5[10]
5 DVDD (I/O supply)
6 AXR1[11]/GP5[11]
7 SPI1_ENA /UART2_RXD/GP5[12]
8 SPI1_SCS[0] /UART2_TXD/GP5[13]
9 SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
10 CVDD (Core supply)
11 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
12 SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
13 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
14 SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
15 DVDD (I/O supply)
16 SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
17 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
18 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
19 EMA_WAIT[0]/ UHPI_HRDY/GP2[10]
20 CVDD (Core supply)
21 EMA_CS[3] /AMUTE2/GP2[6]
22 EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7]
23 EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15]
24 EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
DVDD (I/O supply)
25 EMA_BA[0]/ GP1[14]
26 EMA_BA[1]/ UHPI_HHWIL/GP1[13]
TYPE PULL
(1) (2)
I/O IPD McASP1 serial data
I IPU BOOT[8]
I IPU UART0 receive data
I/O IPU I2C0 serial data
I IPU Timer0 lower input
I IPU BOOT[9]
O IPU UART0 transmit data
I/O IPU I2C0 serial clock
O IPU Timer0 lower output
I/O IPU McASP1 serial data
PWR 3.3-V I/O supply voltage pins
I/O IPU McASP1 serial data
I/O IPU SPI1 enable
I IPU UART2 receive data
I/O IPU SPI1 chip select
O IPU UART2 transmit data
I/O IPU SPI0 chip select
I IPU eQEP0B quadrature input
I IPU BOOT[4]
O IPU UART0 ready-to-send output
PWR 1.2-V core supply voltage pins
I/O IPD SPI0 clock
I IPD eQEP1 index
I IPD BOOT[2]
I/O IPU SPI0 enable
I IPU eQEP0A quadrature input
I IPU BOOT[3]
I IPU UART0 clear-to-send input
I/O IPU SPI1 data/slave-out-master-in
I IPU BOOT[5]
I/O IPU I2C1 serial clock
I/O IPU SPI1 data/slave-in-master-out
I IPU BOOT[6]
I/O IPU I2C1 serial Data
PWR 3.3-V I/O supply voltage pins
I/O IPD SPI1 clock
I IPD eQEP1 strobe
I IPD BOOT[7]
I/O IPD SPI0 data/slave-out-master-in
I IPD eQEP0 index
I IPD BOOT[0]
I/O IPD SPI0 data/slave-in-master-out
I IPD eQEP0 strobe
I IPD BOOT[1]
I IPU EMIFA wait input/interrupt
I/O IPU UHPI ready
PWR 1.2-V core supply voltage pins
O IPU EMIFA Async chip select
O IPU McASP2 mute output
O IPU EMIFA output enable
I/O IPU UHPI data strobe
O IPU EMIFA Async chip select
I IPU BOOT[15]
I/O IPU UHPI chip select
I/O IPU McASP0 serial data
PWR 3.3-V I/O supply voltage pins
O IPU EMIFA bank address
O IPU EMIFA bank address
I/O IPU UHPI half-word identification control
RX-V675/HTR-6066/RX-A730/TSR-6750
Detail of Function
75