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Pin
Function Name
No.
160 AHCLKX1/EPWM0B/GP3[14]
161 CVDD (Core supply)
162 ACLKX1/EPWM0A/GP3[15]
163 AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
164 DVDD (I/O supply)
165 ACLKR1/ECAP2/APWM2/GP4[12]
166 AFSR1/GP4[13]
167 CVDD (Core supply)
168 AXR1[8]/EPWM1A/GP4[8]
169 AXR1[7]/EPWM1B/GP4[7]
170 AXR1[6]/EPWM2A/GP4[6]
171 AXR1[5]/EPWM2B/GP4[5]
172 DVDD (I/O supply)
173 AXR1[4]/EQEP1B/GP4[4]
174 AXR1[3]/EQEP1A/GP4[3]
175 AXR1[2]/GP4[2]
176 AXR1[1]/GP4[1]
(1)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted
in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports
high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus
output), the table reflects the pin function direction for that particular peripheral.
(2)
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3)
122, 123 pin: As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if UART1
boot mode is used.
(4)
134 pin:
Core power supply LDO output for USB PHY. This pin must be connected via a 0.22-mF capacitor to VSS. When the USB peripheral is not
used, the USB_VDDA12 signal should still be connected via a 1-mF capacitor to VSS.
(5)
157 pin:
GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
TYPE
PULL
(1)
(2)
I/O
IPD
eHRPWM0 B output
I/O
IPD
McASP1 transmit master clock
PWR
1.2-V core supply voltage pins
I/O
IPD
eHRPWM0 A output
I/O
IPD
McASP1transmit bit clock
I/O
IPD
Sync input to eHRPWM0 module or sync output to external PWM
I/O
IPD
McASP1 transmit frame sync
PWR
3.3-V I/O supply voltage pins
I/O
IPD
enhanced capture 2/input or auxiliary PWM 2 output
I/O
IPD
McASP1 receive bit clock
I/O
IPD
McASP1 receive frame sync
PWR
1.2-V core supply voltage pins
I/O
IPD
eHRPWM1 A (with high-resolution)
I/O
IPD
McASP1 serial data
I/O
IPD
eHRPWM1 B
I/O
IPD
McASP1 serial data
I/O
IPD
eHRPWM2 A (with high-resolution)
I/O
IPD
McASP1 serial data
I/O
IPD
eHRPWM2 B
I/O
IPD
McASP1 serial data
PWR
3.3-V I/O supply voltage pins
I
IPD
eQEP1B quadrature input
I/O
IPD
McASP1 serial data
I
IPD
eQEP1A quadrature input
I/O
IPD
McASP1 serial data
I/O
IPD
McASP1 serial data
I/O
IPD
McASP1 serial data
RX-V675/HTR-6066/RX-A730/TSR-6750
Detail of Function
79
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