Yamaha RX-V1200 Service Manual page 75

A B
SCHEMATIC DIAGRAM (RX-V1200/RX-V1200RDS/HTR-5490/DSP-AX1200 VIDEO)
1
IC581: LC72722
RDS Decoder
1 5 6
VDDA 3
+ PLL
REFERENCE (57kHz)
VOLTAGE
VSSA 4
VREF
57kHz
MPX IN ANTIALIASING SMOOTHING
2 bpf
FILTER FILTER
(SCF)
DO 20
CL
21
RAM ERROR CORRECTION
DI 22 CCB (24 BLOCK DATA) (SOFT DECISION)
CE
23
CLK(4.332MHz)
T1
7 MEMORY
CONTROL
T2 8
TEST
T3 9
OSC/DIVIDER
T4 10
2
11 16 17 13 12
E-92/J-86 E-92/J-86
B3 C3
3
4
IC601: TK15420M
Video Amp
OUT A 1 8 VCC
–IN A 2 7 OUT B
+ – + –
5
+IN A 3 6 –IN B
VEE 4 5 +IN B
0
4.7
0
0
0 0 4.7
0 4.6
-4.8
0 0
0 0
0 0
0
4.7
0
6
0
0 4.7
0
4.6
0
-4.8
0
0
0
0
0
0
IC611: BU2092
Serial In/Parallel Out Driver
Vss VDD
1 18
DATA 2 17 OE
CLOCK 3 Control 16 Q11
Circuit
LCK 4 15 Q10
Q0 5 14 Q9
Q1 6 13 Q8
Q2 7 12 Q7
Q3 8 11 Q6
Q4 9 10 Q5
7
4.7
4.7
0.9
0
0.2
-0.6
0.9
0.7
0
0
8
9
C D E
CLOCK 14 VDDD
RECOVERY
(1187.5Hz)
15 VSSD
DATA
19 RDS-ID
DECODER
18 SYNC
SYNC/EC
CONTROLLER
24 SYR
SYNC SYNC
DETECT-1 DETECT-2
11.9 4.8
11.9
5.5
0.5
0
5.5
0
4
(see page E-98/J-92)
0 3 4.7
1 0
2
0 0.9
0 2.1
0 4.7
0 2.4
4.7
2.4
2.4
0.9 0 4.3
4.3
-4.8
4.6
0
0.9 0.9
0 6 0 0
7 1.5
5 4.7
0
1.5 0
0.8
-4.8
0
0
0 0
0 4.7
4.7
0 0
0 0
4.0
0
0 4.7 0.9
4.0
-4.8 0
0 0 1.6
0.2 -0.5
0 -4.8
-4.8 -1.6
-4.8
-4.8 -4.8
-0.5
4.7
0
0 0
0 0
0 R688
0 4.7 4.7
-4.8 0
0
0
0 -4.8
(see page E-98/J-92)
5
ON
SCREEN
4.6
1.6
0.9
0.9
1.5
# All voltages are measured with a 10MΩ /V DC electric volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
K KOREA
F G
0 4.9
0 0
0 0
0
0
0
0
0 4.6
-4.9 4.6
0 0
0
0
0
0
0
0
0 0
0
4.9
1.0
0.3
0
0
+5.5V
IC608: TC74HCU04AFEL
Hex Inverters
1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y
to OPE (4) E-94/J-88
G5
2.4 2.4
4.7 4.3
4.3
0
0 1.7 2.1
0 0.8
-0.6
-0.6
0
H I
RX-V1200/RX-V1200RDS/HTR-5490/DSP-AX1200/RX-V2200/DSP-AX2200
IC602, 603: TC74HC4051AP IC607: TC74HC4053AP
Analog Multiplexer/Demultiplexer Analog Multiplexer/Demultiplexer
A
11
B 10
C
VSS
VEE
0X 12
1X 13
0Y
1Y
0Z
1Z
IC702: TC74HC4051AFEL
Analog Multiplexer/Demultiplexer
INHIBIT
6
A
11
B 10
C 9
GND 8
VEE 7
0 13
1 14
2 15
3
12
4
1
4.9
5 5
6 2
0
0
7
4
-4.9
0
-4.9
IC610: LC74781-9798
On Screen Display Controller
CS 9
Serial
SIN 11
parallel command
converter decoder
SCLK 10
RST 23
4.9
4.6
0
-4.9
0
VDD1 24
0
0
Y SELECTOR
VSS1
1
0 4.9
0 0 3 7
0
1
2
0
0
VDD2 12
0 5
CHARA 8
6
0
7
-4.9
0
0 3
0 0
1
2
0 Horizontal
0
OSCIN 6
7
character
-4.9
size
OSCOUT 7
register
Cb SELECTOR
Cr SELECTOR SYNIN 17
Horizontal
character
SEPC 18
0 4.9
size
0 5
0 0 7
SEPOUT 19 register
6
0
0
SEPIN
20
CTRL3 22
IC609: LA7109
75Ω Video Driver
VIN1+
1
NFB1 2
6dB DR
MUTE1 3
VIN2+ 4
6dB DR
NFB2 5
-VCC1 6
IC701: LA7108M
VIN3+ 7 6dB DR
Video Amp
NFB3 8
N.C. 9
VIN1+ 1 16 +VCC
N.C. 10
VIN4+ 11 11
NFB1 2 6dB DR 15 VOUT1
NFB4 12
6dB DR
MUTE1 3 GND
14
MUTE2 13
VIN2+ 4 13 VOUT2
VIN5+
14
6dB DR
6dB DR
NFB2 MUTE2
5 12
NFB5 15
-VCC2 16
-VCC1 6 11 VOUT3
VIN6+ 17
6dB DR
VIN3+ 7 MUTE3
6dB DR 10
NFB6 18
NFB3 8 9 -VCC2
IC751: MM74HC4053SJX
Analog Multiplexer IN/OUT
VCC CY CX BY BX AY AX
16 3 5 1 2 13 12
Logic
Binary to 1
A 11 Level of 2 Decoders
Conversion
with INHBIT
Logic
10
B Level
Conversion Binary to 1
of 2 Decoders
Logic with INHBIT
C 4
Level
Conversion
Binary to 1
Logic
INH 9 Level of 2 Decoders
with INHBIT
Conversion
8 7
GND VSS
J K L
INHIBIT VDD
6 16
INPUT STATES
"ON" CHANNNEL (S)
LEVEL BINARY TO 1-OF-8
INHIBIT C B A
CONVERTER DECODER WITH INHIBIT
0 0 0 0 0X, 0Y, 0Z
9
0 0 0 1 1X, 0Y, 0Z
8
0 0 1 0 0X, 1Y, 0Z
7
0 0 1 1 1X, 1Y, 0Z
SW
X-COM 0 1 0 0 0X, 0Y, 1Z
14
SW
0 1 0 1 1X, 0Y, 1Z
2 SW 0 1 1 0 0X, 1Y, 1Z
15 Y-COM
SW 0 1 1 1 1X, 1Y, 1Z
1
1 X X X NONE
5 SW
Z-COM
4
3 SW
VCC
16
LEVEL BINARY TO 1-OF-8
CONVERTER DECODER WITH INHIBIT
INPUT STATES
"ON" CHANNNEL
INHIBIT C B A
0 0 0 0 0
0 0 0 1 1
SW 3 COM
0 0 1 0 2
SW
0 0 1 1 3
SW 0 1 0 0 4
SW 0 1 0 1 5
0 1 1 0 6
SW
0 1 1 1 7
SW
1 X X X NONE
SW
SW
8-bits
latch
+
Horizontal Vertical Horizontal Vertical Blinking RAM
Display
write
character character display display and inversion
control
size size position position control adress
register
register register register register register counter
Blinking
Horizontal Vertical Horizontal Vertical
and inversion Display
size size dot dot
control RAM
counter counter counter counter
circuit
Blinking Blinking
and inversion and inversion
control control
register register
Character Line Decoder
control control
counter counter
Horizontal
character
Font
size
RAM
register
Character output control
Synchronization
Shift
Timing generator Background control
signal generator register
Horizontal Video output control
character
size
register
4 21 2 3 5 15 13
CTRL1 CTRL2 XtalIN XtalOUT BLANK CVIN CVOUT
+VCC1
36
VOUT1
35
34 GND
33 VOUT2
32 DR CTL2
31 VOUT3
30 MUTE4
29 -VCC4
28 N.C.
27 N.C.
+VCC2
26 26
VOUT4
25
24 GND
VOUT5
23
22 DR CTL1
21 VOUT6
MUTE3
20
19 -VCC3
TO
OUT/IN
AX or AY
YG
TG
OUT/IN
BX or BY
TB
TC
OUT/IN
CX or CY
TG
x: NOT USED
E-96/J-90
O: USED / APPLICABLE