Yamaha RX-V1200 Service Manual page 74

A B
RX-V1200/RX-V1200RDS/HTR-5490/DSP-AX1200/RX-V2200/DSP-AX2200
SCHEMATIC DIAGRAM (DSP)
1
K KOREA
2
DIGITAL OUT INHIBIT
3.3
0 0
4.9 4.9 0
4.9
0.1 0.1
0
0.1 0.1
0.1 0.1
0.1 0.1
4.9 0
4.9
0 0
3.3 0.8 0.1
0.8 0.1
4.9
0.8 0.1
0
0.8 0.1
2.2
3
3.1 2.2
3.9 1.8 0
~
0
1.0 ~
4.8
~ ~
~ ~
~ ~
4.9 0
3.9
0
4.8
3.9
0
4.9 4.9
4.8
3.6
4.9 0
4.9
3.6
3.6
0 0 0
4
0
0
3.9
0 0
4.8
0
0 0 4.9 0
DUTY CORRECTOR
4.9 4.9
0 0 0
3.1 0 4.9
2.6 0.4
0
0
0
DIGITAL IN
0 0 0
4.9
3.1 0.4 0
2.6
5 0
LEVEL CONVERT & SIGNAL DETECT
0 0 0 0
4.9 4.9
&4
3.3 0 3.3 4.9
0 0 3.3 0
3.3 0 3.3 3.3
3.3 3.3 3.3
3.3
3.3 3.3 3.3 3.3
6
3.3 0 3.3 3.3
3.3 3.3 3.3 3.3
3.3 0 3.3 3.3
3.3
3.3 0
0 3.3 3.3
0 3.3 3.3 3.3
4.9 3.3 3.3
4.8
0 3.3 3.3
3.3 0 0
0
256K
3.3
0
0
SRAM
3.3 3.3
3.3 0
3.3 3.3
3.3 3.3
3.3 0
3.3 3.3
3.3 3.3
4M
FLASH
7
IC516: µPC29M33T-E1 IC525: CS493292-CLR
Voltage Regulator Audio Decoder
1 INPUT
Safety Drive
Limiter
Amp.
A0, SCCLK 7
OUTPUT
3 DATA7, EMAD7, GPIO7 8
DATA6, EMAD6, GPIO6 9
DATA5, EMAD5, GPIO5 10
DATA4, EMAD4, GPIO4 11
8
VD2 12
DGND2 13
Excessive Electric
DATA3, EMAD3, GPIO3 14
Current Protection
DATA2, EMAD2, GPIO2 15
2 GND
DATA1, EMAD1, GPIO1 16
DATA0, EMAD0, GPIO0 17
IC517: PQ025EZ5MZP
Regulator
Vin 1 3 Vo
2 Vc
5
9
E-95/J-89
GND
C D E
RX-V1200/RX-V1200RDS/HTR-5490/DSP-AX1200: E-92/J-86
E-94/J-88
I5
&4 IC528 MBM29F400BC-70PFTN
MX29F400BTC-70
REGULATOR
2.5 4.9
3.3 4.9
0 2.5 4.7 4.9
4.9
2.5 3.3
0
0 0
0 DSP/DOLBY/DTS
2.5
0.4
0
3.9
Point 3 Pin 2 of IC514
0
0
0
3.3
0
4.7
2.7
0 2.7
0
4.9
4.8
0
0
0
3.9
0
3.9
3
3.9
0
2.5
3.3
0
2.7 1.3
1.7
0
2.7 1.7
2.7 0
1.6
3.3 3.3
2.5
0
0 0.2
0
0
2.6 0
PLD
3.3
2.6
0 3.3
0
0 3.3
2.5 3.3
2.7 3.3
3.3 3.3
0 3.3
1.3 3.3
1.3 3.3
0
4.9 3.3
0 3.3
0 0
4.8 3.3
0.5 3.3
3.3 0
4.8 0
0 3.3
4.9
36 8 9 10 11 14 15 16 17 18 5 4 19
Parallel or Serial Host Interface
39 AUDATA2 27
38 DC Compressed
Data Input
37 DD 28
Interface Frame
36 RESET
Shifter
29 24-Bit
35 AGND
DSP Processing
34 VA Input
RAM RAM
33 FILT1 Buffer RAM Output
Program Data
25
32 FILT2 Digital Controller
Memory Memory Buffer
Audio
31 CLKSEL
26
RAM RAM
Input
30 CLKIN
Program Data
Interface
29 CMPREQ, LRCLKN2 22
Memory Memory
RAM Input
Buffer
STC
30
PLL
Clock Manager
31
32 33 34 35 24 13 2 23 12 1
F G
RX-V2200/DSP-AX2200: E-93/J-87
# All voltages are measured with a 10MΩ /V DC electric volt meter.
D1
# Components having special characteristics are marked s and must be
replaced with parts having specifications equal to those originally
installed.
# Schematic diagram is subject to change without notice.
MAIN L (ANALOG IN)
0 0
3.3 0
1.6 3.3
3.3 3.3
1.7 2.6
1.3 2.6
1.7 2.6
0
2.6
0 2.6
0.1
3.3 0
0.1
0 5.0
0.1
0 5.0
2.5
3.3 0
0
0 0
3.3
0
3.3
CENTER
3.3
0
3.3
3.3
3.3
3.3
3.3
0 0
0 3.3 0
0 1.7 3.3
3.3 3.3 3.3
0.7
1.7 2.6
3.3 0.7 2.6
0 1.7 2.6
0.5
0
0 0
3.3 0
0
5.0
0 0 5.0
3.3 0
0 0
1.7
1.7
1.6
D/A CONVERTER
0
0
0
2.5
0
0
3.3
0
0 2.5
CODEC
0 2.5
1.7 2.5
1.7 2.5
2.5
3.3
2.5
0
2.5
0.5
2.5
~
0 2.5
2.5
0
DECODER
1.7
1.7
0
2.5
1.3
2.7
3.8
2.7
3.3
FRONT L
4.9
4.9
REAR L
3.8
4.9
0
IC527: CY62256LL
Static RAM
7 6 20 21
37
38
I/O
A 0
10 INPUT
A
9 BUFFER I/O
1
A
8
44 A I/O
7 2
43 A
6
I/O
A 512x512 3
42 5
A ARRAY I/O
Output 4 4
39
A
3
Formatter
40 A I/O
2 5
41
POWER I/O
6
CE
3
DOWN
I/O
WE COLUMN 7
DECODER
OE
H I
IC501, 502: TC74HCU04AF
Hex Inverters
1A
1Y
2A
2Y
3A
3Y
GND
IC508, 524: AK4393-VF-E2
D/A Converter
LRCK
BICK
11.8
SDATA
2.4K
0
0 PD
0
0
2.4K
0
SMUTE
0
-11.4 -11.3
0
0 DFS
0
0
-11.3
2.4K
0
0
0
2.4K
0
-11.9
LIN+
LIN-
RIN+
11.8
RIN-
0
0
0 LOUT1
0
-11.9
0
3.3
ROUT1
-11.4 -11.3
0
0
0 LOUT2
ROUT2
0
LOUT3
0
0
ROUT3
5.0 5.0 5.0 5.0
2.5
11.8 11.8
2.5 2.5
2.5 2.5
2.5 2.5 2.5
2.5 2.5 INPUTS
2.5 2.5 2.5
2.5 2.5
2.5 2.5
2.5
2.5 2.5
0
-11.9 -11.9
0 0 0
11.8
0
2.9 2.8
0 0
0
0
IC515: MSM514260C-60JS
0.6
4Mbit DRAM
0
0.3
2.9 0
0
0
0.6
RAS 14
0 2.8
0 0
2.8 0
0 -11.9
LCAS 29
11.8
UCAS 28
0
2.8 2.8
0 0
0
0
0.6
6.2K
0
3.3
0
2.8
0 0
0.6
6.2K A0~A8
0 2.8
0 0
2.8
0
0
-11.9
11.8
0
0
0
-11.4
0 0
0 0
0
-11.3 0
0
0
VCC 20
0
0
-11.3
0 0
0
0 VSS
-11.4 21
0
0
-11.9
IC528: MBM29F400BC-70
IC526: XC9572XL-10TQ100C 4Mbit Flash Memory
CPLD
3
JTAG
JTAG Port In-System Programming Controller
1
Controller
VCC
VSS
54
Function
I/O
Block 1
18
WE
Macrocells
I/O
1 to 18
BYTE
I/O
RESET
I/O
54
Function
Block 1
18
Macrocells
1 to 18
CE
OE
I/O
I/O
Blocks
I/O 54
Function
Block 1
18
I/O
Macrocells
1 to 18
I/O
3
I/O/GCK
54
Function
1
Block 1
I/O/GSR
18
Macrocells
2 A0 to A17
I/O/GTS 1 to 18
A-1
J K
IC503: TC74HCT00AF IC509, 518~523: µPC4570G2
Quad 2-Input Nand Gate Dual OP-Amp
1A 1 14 Vcc
1 14 VCC
OUT 1 1 8 +V CC
1B 2 13 4B
2 13 6A
–IN 2 7 OUT
1Y 3 12 4A 1 2
+ – + –
3 12 6Y 2A 4 11 4Y
+IN 3 6 –IN
1 2
2B 5 10 3B
4 11 5A
–V 4 5 +IN
CC 2
2Y 6 9 3A
5 10 5Y GND 7 8 3Y
6 9 4A
7 8 4Y
DIF0 DIF1 DIF2 DVDD DVSS DEM0 DEM1 AVDD AVSS
12 13 14 2 1 10 11 18 19
15 BVSS
7
Serial Input De-emphasis
5
Interface Control VCOM
24
6
De-emphasis 8X 23 AOUTL+
4 S C F
Soft Mute Interpolator Mo d u l a t o r AOUTL-
22
8
De-emphasis 8X 21 AOUTR+
S C F
Soft Mute Interpolator Mo d u l a t o r 20 AOUTR-
9
Control Register Clock DMder
25 3 26 27 28 17 16
CCLK CDTI MCLK CKS0 CKS1 CKS2 VREFH VREFL
CS P/S
IC510: AK4527BVQ IC512: TC74HCT08AF
24bit CODEC Quad 2-Input And Gate
1A 1 14 Vcc
Audio
30
ADC HPF I/F 1B 2 13 4B
29
1Y 3 12 4A
32
ADC HPF
31
2A 4 11 4Y
2B 5 10 3B
LPF DAC DATT MCLK 39 MCLK
27
2Y 6 9 3A
LRCK
6 LRCK
BICK BICK
4 GND 7 8 3Y
28 LPF DAC DATT
10 DAUX
25 LPF DAC DATT
Format
Converter
26 LPF DAC DATT
6DOUT
1 SDOS
LPF DAC DATT
23
SDTO
9
SDIN1
LPF DAC DATT 6 SDTI1
24
SDIN2 SDTI2
7
SDIN3 8 SDTI3
IC513: NJM2904M
Dual OP-Amp
V–
Q6
Q2 Q3 Q5
–
Q1 Q4
Q7
OUTPUT
Q13
+
Q11
Q12
Q10
Q8 Q9
WE OE
13 27
Timing
Generator
I/O
Controller
Output
8 8
I/O Buffers
Controller
DQ1~
DQ8
Column
Input
9 Address 9 Column Decoders
8
8
Buffers
Buffers
I/O
Internal
Sense Amplifiers 16 16
Refresh Selector
Addess
Control Clock
Counter
Input
8
8
Buffers
Row
Row
DQ9~
9 Address 9 Word
Deco- Memory
DQ16
Buffers
Drivers Cells
ders
Output
8
8 Buffers
On Chip
VBB Generater
RY/BY DQ0 to DQ15
RY/BY
Buffer
Erase Voltage Input/Output
Generator Buffers
State
Control
Command
Register
Program Voltage
Generator Chip Enable STB
Data Latch
Output Enable
Logic
Y-Decoder Y-Gating
STB
Timer for
Address
Low Vcc Detector
Program/Erase
Latch
X-Decoder Cell Matrix
L