Sharp UP-3300 Service Manual page 48

Pin Signal
Symbol
No. name
34 NC NC
35 CS1 S A1
36 CLK/TRG3 S TM1
37 CLK/TRG2 S TM0
38 NC NC
39 NC NC
40 CLK/TRG1 S INTS
41 CLK/TRG0 VCC
42 NC NC
43 +5V VCC
44 NC NC
2-6. µPD71037
DMA CONTROLLER
The µPD71037 is a direct memory access controller (DMAC) for the
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to mem-
ory as well.
1) FEATURES
•
The clock speed is 10 MHz, twice that of the µPD8237A-5 (clock
speed of 5 MHz).
•
Each of the four DMA channels can be operated independently.
•
Each channel can be self-initialized.
•
Data is transferrable from memory to memory.
•
Data in memory can independently initialized by block.
•
High speed data transfer:
3.2 MB/sec. (clock seed of 10 MHz, normal transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
•
The number of DMA channels can directly be expanded
(Expansion mode).
•
END input when data transfer is finished.
•
Software DMA request available.
•
CMOS
•
Low power consumption
2) Pin configuration
READY 1
HLDAK 2
ASTB 3
AEN 4
HLDRQ 5
µPD71037GB-3B4
NC 6
CS 7
CLK 8
RESET 9
DMAAK2 1 0
DMAAK3 1 1
In/Out Function
— NC
In Channelselect signal
In External clock / timer signal
In External clock / timer signal
— NC
— NC
In External clock / timer signal
In +5V
— NC
— +5V
— NC
33
32
31
30
29
28
27
26
25
24
23
3) Pin configuration
Pin
Symbol
No.
1 READY
2 HLDAK
3 ASTB
4 AEN
5 HLDRQ
6 NC
7 CS
8 CLK
9 RESET
10 DMAAK2
11 DMAAK3
12 DMARQ3
13 DMARQ2
14 DMARQ1
15 DMARQ0
16 GND
17 NC
18 A15/D7
19 A14/D6
20 A13/D5
21 DMAAK1
22 DMAAK0
23 A12/D4
24 A11/D3
25 A10/D2
26 A9/D1
27 A8/D0
28 NC
29 VDD
30 A0
31 A1
32 A2
33 A3
34 NC
35 END / TC
36 A4
37 A5
38 A6
39 A7
40 IORD
41 IOWR
A3
42 MRD
A2
43 MWR
A1
44 NC
A0
VDD
NC
A8/D0
A9/D1
A10/D2
A11/D3
A12/D4
7 – 15
Signal
In/Out
name
READY In Ready signal
HLDAK In Hold acknowledge signal
S ASTB Out Address strobe signal
S AEN Out Address enable signal
HLDRQ Out Hold request signal
NC — NC
CS In Chip select signal
CLK In Clock
SRNRESET In Reset signal
S DACK2 Out DMA acknowlidge signal
S DACK3 Out DMA acknowlidge signal
S DRQ3 In DMA request signal
S DRQ2 In DMA request signal
S DRQ1 In DMA request signal
S DRQ0 In DMA request signal
GND — GND
NC — NC
S D7 In/Out Data bus
S D6 In/Out Data bus
S D5 In/Out Data bus
S DACK1 Out DMA acknowlidge signal
S DACK0 Out DMA acknowlidge signal
S D4 In/Out Data bus
S D3 In/Out Data bus
S D2 In/Out Data bus
S D1 In/Out Data bus
S D0 In/Out Data bus
NC — NC
VCC — +5V
S A0 In Address bus
S A1 In Address bus
S A2 In Address bus
S A3 In Address bus
NC — NC
TC In/Out End / Terminal cut signal
S A4 In Address bus
S A5 In Address bus
S A6 In Address bus
S A7 In Address bus
S IOR In/Out I/O read signal
S IOW In/Out I/O write signal
S MRD Out Memory read signal
NC — NC
NC — NC
Function