Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait
states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 25: A5W2
Bit 24: A5W1
0
0
1
1
0
1
Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Bit 22: A5B2
Bit 21: A5B1
0
0
1
1
0
1
Bit 23: A5W0
Inserted Wait States
0
0
1
1
0
2
1
3
0
6
1
9
0
12
1
15 (Initial value)
Wait States Inserted from
Second Data Access Onward
Bit 20: A5B0
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7 (Initial value)
Description
First Cycle
Description
Burst Cycle (Excluding First Cycle)
Rev. 6.0, 07/02, page 345 of 986
RDY Pin
RDY
RDY
RDY
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RDY Pin
RDY
RDY
RDY
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled