Interrupt Mask Clear Register 00 (Intmskclr00) (Sh7750R Only); Bit Assignments Of Intreq00, Intmsk00, And Intmskclr00 (Sh7750R Only); Table 19.8 Bit Assignments - Hitachi SH7750 Hardware Manual

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Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)

The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt

requests. INTMSKCLR00 is a 32-bit write-only register.

Initial value:

Initial value:

Bit 31 to 0    Interrupt Mask Clear: Each bit selects whether or not to clear the masking of the

interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt

sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00

(SH7750R Only).

Bits 31 to 0

Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00

(SH7750R Only)

The relationship between the bits in these registers and interrupt sources is as shown below.

31 to 10, 7 to 0

Masking of interrupt requests from the source that corresponds to the

bit is not changed

Masking of interrupt requests from the source that corresponds to the

bit is cleared

Rev. 6.0, 07/02, page 767 of 986

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