Oc Address Array; Figure 4.13 Memory-Mapped Ic Data Array - Hitachi SH7750 Hardware Manual

31
Address field
1 1 1 1 0 0 0 1
31
Data field
L : Longword specification bits
: Reserved bits (0 write value, undefined read value)
4.6.3

OC Address Array

The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed is specified in the address field,
and the write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is
specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry
specification. In RAM mode (CCR.ORA = 1), the OC's address arrays are only accessible in the
memory-mapped cache area, and bit [13] is used to specify the way. For details about address
mapping, see section 4.6.5. The address array bit [3] association bit (A bit) specifies whether or
not association is performed when writing to the OC address array. As only longword access is
used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
The following three kinds of operation can be used on the OC address array:
1. OC address array read
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
way and the entry set in the address field. In a read, associative operation is not performed
regardless of whether the association bit specified in the address field is 1 or 0.
2. OC address array write (non-associative)
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the way and the entry set in the address field. The A bit in the address field should be cleared
to 0.
24 23

Figure 4.13 Memory-Mapped IC Data Array

13 12
Way
Longword data
Rev. 6.0, 07/02, page 119 of 986
5 4 2 1 0
Entry L
0