22.3
AC Characteristics
In principle, SH7750 Series input should be synchronous. Unless specified otherwise, ensure that
the setup time and hold times for each input signal are observed.
Table 22.17 Clock Timing (HD6417750RBP240)
Item
Operating
CPU, FPU, cache, TLB
frequency
External bus
Peripheral modules
Table 22.18 Clock Timing (HD6417750RF240)
Item
Operating
CPU, FPU, cache, TLB
frequency
External bus
Peripheral modules
Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)
Item
Operating
CPU, FPU, cache, TLB
frequency
External bus
Peripheral modules
Table 22.20 Clock Timing (HD6417750RF200)
Item
Operating
CPU, FPU, cache, TLB
frequency
External bus
Peripheral modules
Table 22.21 Clock Timing (HD6417750SF200)
Item
Operating
CPU, FPU, cache, TLB
frequency
External bus
Peripheral modules
Rev. 6.0, 07/02, page 842 of 986
Symbol
Min
f
1
1
1
Symbol
Min
f
1
1
1
Symbol
Min
f
1
1
1
Symbol
Min
f
1
1
1
Symbol
Min
f
1
1
1
Typ
Max
—
240
—
120
—
60
Typ
Max
—
240
—
84
—
60
Typ
Max
—
200
—
100
—
50
Typ
Max
—
200
—
84
—
50
Typ
Max
—
200
—
67
—
50
Unit
MHz
Unit
MHz
Unit
MHz
Unit
MHz
Unit
MHz