Motorola DSP56156 Manual page 33

15 14 13 12 11 10
TL TL S1L S1L S0L S0L HL HL CL CL IBL IBL IBL IAL IAL IAL
Figure 1-8 Interrupt Priority Register IPR (Address X:$FFDF)
Table 1-2
Status Register Interrupt Mask Bits
I1 I0 Exceptions
Permitted
0 0 IPL 0,1,2,3
0 1 IPL 1,2,3
1 0 IPL 2,3
1 1 IPL 3
Table 1-4
External Interrupt Trigger Mode Bits
IxL2
0
1
priority level of the interrupts) has control bits for the two external interrupt pins and each
of the on-chip peripherals (see Figure 1-8, Table 1-2, and Table 1-4). There are 30 inter-
rupts available and two reserved on the DSP56156. Table 1-6 shows each of these inter-
rupts with their respective starting address and Interrupt Priority Level (IPL). The four level
three interrupts are not maskable and if two or more are simultaneously issued, their pri-
ority is (1) Hardware Reset, (2) Illegal Instruction, (3) Stack Error, and (4) the SWI instruc-
tion. The reserved interrupt is not available for use. The PCU contains five directly
addressable registers in addition to the program counter (PC). These are the loop address
(LA), loop counter (LC), status register (SR), operating mode register (OMR), and stack
pointer (SP). The PC also contains a 15 level, 32-bit wide system stack memory. The 16-
1 - 12
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
9 8 7 6 5
Exceptions
Masked
None
IPL 0
IPL 0,1
IPL 0,1,2,
Trigger Mode
Level
Negative Edge
DSP56156 OVERVIEW
4 3 2 1 0
Table 1-3
Interrupt Priority Level Bits
xxL1 xxL0
0 0
0 1
1 0
1 1
IRQA mode
IRQB mode
Codec IPL
Host IPL
SSI0 IPL
SSI1 IPL
TM IPL
Enabled IPL
No -
Yes 0
Yes 1
Yes 2
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