Motorola DSP56156 Manual page 179

dc $577b
; Biquad stage no. 4
dc -$14e9
dc $f302
dc $3998
dc $3080
; temporary storage for I/O test purpose
flag dc 0
inbuf dc 0
outbuf dc 0
pre_out dc 0
;*******************************************************
;
org p:$0
jmp start
org p:$2E
jsr codec
org p:start
ori #$03,mr
move #>0,x0
move x0,x:bcr
move #$c408,x0
move x0,x:cocr
move #plcr,r0
move #>$6f,x0
move x0,x:(r0)
lock bftsth #$8000,x:(r0)
bcc lock
bfset #$4000,x:(r0)
ori #$80,omr
move #$00c0,x0
move x0,x:ipr
andi #$fc,mr
lo bra lo
;***********************************
; codec interrupt routine
;***********************************
codec move x:crx,a
move #w,r0
move #w+Nw+Nw,r3
move #w+Nw+Nw+3,r1
move #-1,n0
move #4,n1
move #2,n3
bfset #$800,sr
asr a
move a,y0
mpy y0,x0,a
move x:(r0)+,y0
do #nstages,_end1
6 - 64
APPLICATION EXAMPLES
x:(r3)+,x0
x:(r3)+,x0
DSP56156 ON-CHIP SIGMA/DELTA CODEC
; n1_3 = 1.366865914/2
; d2_4 = 0.3267375315/2
; d1_4 = -0.2029987284/2
; n2_4 = 0.8999033261/2
; n1_4 = 0.7578121768/2
;input data buffer
;output data buffer
;output buffer for interpolation
;reset interrupt vector
;jump to main routine
;codec interrupt vector
;codec interrupt service routine
;main program start address
;disable all interrupts
;Zero wait (no delay on bus access)
;coie=coe=1;msg0=0(-6dB);CRS=0,MUT~=1;V3-V0=$8
;set Codec Control Register
;get the PLL control register address
;divide by 16, 32M/16=2M for Codec clock
;Core master clock Fosc = 32/(15+1)x4x(6+1)=56M
;set PLL control register(not include bit4-7)
;check PLL register for VCO lock?
;if not, loop around until it is locked
;enable PLL clock
;disable clock out, may be quite for codec and PLL
;codec IPL enable level 2
;enable chip PL to level 2
;loop forever for test (wait for interrupt)
; read data from a/d
; enable Scale Up mode
; a = x(n)/2,x0=g/2
; y0 = x(n)
; a = g/2 * x(n)
; y0 = w(n-2), x0 = a2/2
MOTOROLA