Motorola DSP56156 Manual page 260

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PLCR
to the desired DSP core operating frequency. The PLL can also be disabled (PLLE=0), in
which case the core will directly use the 9.72 MHz clock and will run at 4.8 MIPS.
9.2.3 Example Three
In the third example, the 4-bit input divider divides the input clock (16.8MHz) by 10, pro-
viding a 1.68 MHz clock to the Σ∆ codec and to the PLL. The PLL can multiply the 1.68
MHz clock up to the desired DSP core operating frequency. The PLL can also be dis-
abled (PLLE=0), in which case the core will directly use the 16.8 MHz clock and will run
at 8.4 MIPS.
9.3 ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PLCR
The Clock Synthesis Control Register, PLCR, is a 16-bit read/write register used to direct
the on-chip clock synthesis operation. The PLCR controls two programmable dividers
and can enable or disable the on-chip PLL. The PLCR control bits are described in the
following sections. All PLCR bits are cleared by DSP hardware reset. Software reset
does not affect this register.
9.3.1 PLCR Input Divider Bits (ED3-ED0) Bits 0-3
The four input divider bits are used to divide the input clock frequency by any number
between 1 and 16. The divider output is used as an input clock for the on-chip codec sec-
tion and for the on chip PLL as shown in Figure 9-1. If ED is the value contained in the
four bits, the external clock is divided by ED+1. Any time a new value is written to the ED
bits, the LOCK bit is cleared.
Care should be taken not to exceed the codec maximum operating frequency and to
remain in the frequency stability domain of the PLL.
9.3.2 PLCR Feedback Divider Bits (YD3-YD0) Bits 4-7
The four feedback divider bits, YD3-YD0, cause the down counter in the feedback loop
to divide by the value YD+1 where YD is the value contained in YD3-YD0. Changing
these bits requires a time delay for stabilization so that the Voltage Controlled Oscillator
(VCO) can relock. Any time a new value is written to the YD bits, the LOCK bit is cleared.
The resulting DSP core system clock must be within the limits specified by DSP56156
technical data sheet.
9.3.3 PLCR Clockout Select Bits (CS1-CS0) Bits 10-11
The two Clockout Select bits, CS1-CS0, determine the frequency put on the CLCKO pin
when the CD bit in the OMR register is cleared (CD=0). After hardware reset, the internal
MOTOROLA ON-CHIP FREQUENCY SYNTHESIZER 9 - 7