Motorola DSP56156 Manual page 306

EXTAL
P.L.L.
CLKO
On-chip Frequency Synthesis Control/Status Register (PLCR) ADDRESS X:$FFDC
15 14 13
LOCK PLLE PLLD GSM CS1 CS0
LOCK 0
1
PLLE PLLD 00
01
10
11
GSM 0
1
CS1-CS0 0
CLKO 1
Select 2
3
ED3-ED0 $0
Clock $1
Input $2
Divider $3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
YD3-YD0 $0
VCO $1
Down $2
Counter $3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
Figure C-7 On-chip Frequency Synthesizer Programming Model Summary
C - 22
DSP56156 Phase Locked Loop Programming Sheet
÷ 6.5
GSM
÷ 1 to ÷ 16
ED3-ED0
CS1-CS0
÷ 2
12 11 10 9
**
PLL unlocked
PLL locked
PLL active but not used as Fosc
PLL powered down
PLL active and used as Fosc
Reserved
Output of the 4 bit divider selected as codec clock input
Output of the 6.5 divider selected as codec clock input
PH0 output to CLKO when enabled by the CD bit (bit 7) of the OMR
reserved
Fext output to CLKO when enabled by the CD bit (bit 7) of the OMR
Fext/2 output to CLKO when enabled by the CD bit (bit 7) of the OMR
Divide the input clock by 1
Divide the input clock by 2
Divide the input clock by 3
Divide the input clock by 4
Divide the input clock by 5
Divide the input clock by 6
Divide the input clock by 7
Divide the input clock by 8
Divide the input clock by 9
Divide the input clock by 10
Divide the input clock by 11
Divide the input clock by 12
Divide the input clock by 13
Divide the input clock by 14
Divide the input clock by 15
Divide the input clock by 16
PLL multiplies the clock by 4
PLL multiplies the clock by 8
PLL multiplies the clock by 12
PLL multiplies the clock by 16
PLL multiplies the clock by 20
PLL multiplies the clock by 24
PLL multiplies the clock by 28
PLL multiplies the clock by 32
PLL multiplies the clock by 36
PLL multiplies the clock by 40
PLL multiplies the clock by 44
PLL multiplies the clock by 48
PLL multiplies the clock by 52
PLL multiplies the clock by 56
PLL multiplies the clock by 60
PLL multiplies the clock by 64
PROGRAMMING SHEETS
CODEC
PHASE
Filter VCO
COMP.
4-bit VCO down counter
÷ 1 to ÷ 16
÷4
YD3-YD0
internal phase PH0 at Fosc
8 7 6 5 4
** YD3 YD2 YD1 YD0
PLLE=1
Fosc
PLLE=0
3 2 1 0
ED3 ED2 ED1 ED0
MOTOROLA