Interface Control Register (Icr); Host-Side Register Map - Motorola DSP56303 User Manual

Host Programmer Model
force interrupt handlers (for example, ESSI, SCI,
control or debugging operations.
Note: When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the HI08
configuration remains unchanged in Stop mode, the core cannot be restarted via the
HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you
provide some other mechanism to exit stop mode.
Host
Address
0
1
2
3
4
5
6
7
6.7.1

Interface Control Register (ICR)

The ICR is an 8-bit read/write control register by which the host processor controls the HI08
interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register,
which allows the use of bit manipulation instructions on control register bits. Hardware and
software reset clear the ICR bits.
6-24
Table 6-14. Host-Side Register Map
Big Endian
HLEND = 0
ICR
CVR
ISR
IVR
00000000
RXH/TXH
RXM/TXM
RXL/TXL
7 6 5
INIT HLEND HF1
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-15. Interface Control Register (ICR)
DSP56303 User's Manual
, interrupt routines), and perform
IRQA IRQB
Little Endian
HLEND = 1
ICR
CVR
ISR
IVR
00000000
RXL/TXL
RXM/TXM
RXH/TXH
4 3 2 1
HF0 HDRQ TREQ RREQ
Register Name
Interface Control
Command Vector
Interface Status
Interrupt Vector
Unused
Receive/Transmit
Data
0