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7.6.2
Port Direction Registers (PRRC and PRRD)
The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO
signals when they are enabled by the associated Port Control Register (PCRC or PCRD,
respectively). When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO)
signal. When PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI)
signal. Either a hardware
PRRD bits.
23
22
21
11
10
9
Note:
For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals
are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs
are PRC[5–0]. The corresponding direction bits for Port D GPIOs are PRD[5–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
The following table summarizes the ESSI port signal configurations.
PCRC/PCRD[i]
1
0
0
X: The signal setting is irrelevant to the Port Signal[i] function.
signal or a software RESET instruction clears all PRRC and
RESET
20
19
18
8
7
6
Table 7-6. ESSI Port Signal Configurations
PRRC/PRRD[i]
X
0
1
Enhanced Synchronous Serial Interface (ESSI)
17
16
15
5
4
3
PRx5
PRx4
PRx3
Port Signal[i] Function
ESSI0/ESSI1
Port C/Port D GPI
Port C/Port D GPO
GPIO Signals and Registers
14
13
12
2
1
0
PRx2
PRx1
PRx0
7-37
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