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Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
3–2
DDS[1–0]
0
1–0
DSS[1–0]
0
4.8
Device Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family
members. It specifies the derivative number and revision number of the device. This
information is used in testing or by software. Figure 4-10 shows the contents of the IDR.
Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on.
.
23
Reserved
$00
Figure 4-10. Identification Register Configuration (Revision E)
DMA Destination Space
Specify the memory space referenced as a destination by the DMA.
NOTE: In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 8, Instruction Cache , and Chapter 11, Operating Modes and Memory
Spaces ).
DDS1
0
0
1
1
DMA Source Space
Specify the memory space referenced as a source by the DMA.
NOTE: In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 8, Instruction Cache , and Chapter 11, Operating Modes and Memory
Spaces ).
DSS1
0
0
1
1
16
15
Revision Number
$5
Core Configuration
Device Identification Register (IDR)
Description
DDS0
DMA Destination Memory Space
0
X Memory Space
1
Y Memory Space
0
P Memory Space
1
Reserved
DSS0
DMA Source Memory Space
0
X Memory Space
1
Y Memory Space
0
P Memory Space
1
Reserved
12
11
Derivative Number
$303
0
4-37
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