3.7.1
Operations in Standby Mode
This section describes CPU and peripheral function operation in standby mode.
■
Operations in Standby Mode
Table 3.7-1 Operations of the CPU and Peripheral Functions in Standby Mode
Function
Clock
Instruction
CPU
ROM
RAM
I/O port
Time-base timer
Watchdog timer
8-bit PWM timer/counter
8/16-bit capture timer/counter
Peripheral
UART
function
8-bit serial I/O
12-bit PPG
Buzzer
External interrupt 1 and 2
A/D converter
● State of pins in standby mode
The state of most I/O pins can remain the same as those set immediately before transition to stop mode or
set to Hi-Z using the pin state setting bit in the standby control register (STBC: SPL), regardless of clock
mode.
Note:
For details on pin states in standby mode, see "APPENDIX E Pin State of the MB89202/F202RA
Series ".
RUN
Sleep
Active
Active
Active
Stopped
Active
Holding
Active
Holding
Active
Active
Active
Stopped
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CHAPTER 3 CPU
Stop
Stop
(SPL=0)
(SPL=1)
Stopped
Stopped
Stopped
Stopped
Holding
Holding
Holding
Hi-Z
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Active
Active
Stopped
Stopped
63