Time-Base Timer Control Register (Tbtc) - Fujitsu F2MC-8L F202RA Hardware Manual

5.3

Time-base Timer Control Register (TBTC)

The time-base timer control register (TBTC) selects a time interval, clears the counter,
controls interrupts, or checks the status.
■
Time-base Timer Control Register (TBTC)
Address
bit7 bit6 bit5
000A
TBOF TBIE
H
R/W R/W
R/W : Readable/Writable
: Unused
: Initial value
Figure 5.3-1 Time-base Timer Control Register (TBTC)
bit4 bit3 bit2
TBC1 TBC0 TBR
R/W R/W R/W
TBR
0
1
"1" is always read.
TBC1 TBC0
0 0
0 1
1 0
1 1
F : Oscillation frequency
CH
TBIE
0 The interrupt request output is disabled.
1 The interrupt request output is enabled.
TBOF
0 The specified bit has not overflowed. This bit is cleared.
1
The specified bit has overflowed.
bit1 bit0
Initial value
00---000
Time-base timer initialization bit
Read
The time-base timer counter is cleared.
Nothing is changed and affected.
Time interval selection bits
13
/
2 F
CH
15
/
2 F
CH
18
/
2 F
CH
22
/
2 F
CH
Interrupt request enable bit
Overflow interrupt request flag bit
Read
Nothing is changed and affected.
CHAPTER 5 TIME-BASE TIMER
B
Write
Write
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