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6: The Bus Interface
Table 6-7 shows active byte lanes for big-endian systems.
Table 6-7 Active byte lanes for a 32-bit big-endian data bus
Transfer size
Word
Halfword
Halfword
Byte
Byte
Byte
Byte
6.7
Arbitration
The arbitration mechanism is described fully in the
mechanism is used to ensure that only one master has access to the bus at any one time. The
arbiter performs this function by observing a number of different requests to use the bus and
deciding which is currently the highest priority master requesting the bus. The arbiter also
receives requests from slaves that want to complete SPLIT transfers.
Any slaves that are not capable of performing SPLIT transfers do not have to be aware of the
arbitration process, except that they need to observe the fact that a burst of transfers might
not complete if the ownership of the bus is changed.
6.7.1
HBUSREQ
The bus request signal is used by a bus master to request access to the bus. Each bus master
has its own HBUSREQ signal to the arbiter and there can be up to 16 separate bus masters
in any system.
6.7.2
HLOCK
The lock signal is asserted by a master at the same time as the bus request signal. This
indicates to the arbiter that the master is performing a number of indivisible transfers and the
arbiter must not grant any other bus master access to the bus once the first transfer of the
locked transfers has commenced. HLOCK must be asserted at least a cycle before the address
to which it refers, to prevent the arbiter from changing the grant signals.
6.7.3
HGRANT
The grant signal is generated by the arbiter and indicates that the appropriate master is
currently the highest priority master requesting the bus, taking into account locked transfers
and SPLIT transfers.
A master gains ownership of the address bus when HGRANT is HIGH and HREADY is HIGH
at the rising edge of HCLK.
6-12
Address
DATA[31:24]
offset
0
0
2
-
0
1
-
2
-
3
-
DATA[23:16]
DATA[15:8]
-
-
-
-
-
-
-
-
AMBA Specification (Rev 2.0)
EPSON
DATA[7:0]
-
-
-
-
. This
ARM720T CORE CPU MANUAL
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