Figure 2-4 Register Organization In Thumb State - Epson ARM720T Core Cpu Manual

2: Programmer's Model
2.6.2 The Thumb state register set
The Thumb state register set is a subset of the ARM state set. You have direct access to:
• eight general registers, (r0–r7)
• the PC
Stack Pointer
• a
Link Register
• a
• the CPSR.
There are banked SPs, LRs, and
mode. This is shown in Figure 2-4.
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
CPSR
= banked register
2-6
register
(SP)
(LR)
Saved Program Status Registers
Thumb state general registers and program counter
FIQ Supervisor
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
SP_fiq SP_svc
LR_fiq LR_svc
PC PC
Thumb state program status registers
CPSR CPSR
SPSR_fiq SPSR_svc

Figure 2-4 Register organization in Thumb state

Abort
r0
r1
r2
r3
r4
r5
r6
r7
SP_abt
LR_abt
PC
CPSR
SPSR_abt
EPSON
(SPSRs) for each privileged
IRQ Undefined
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
SP_irq SP_und
LR_irq LR_und
PC PC
CPSR CPSR
SPSR_irq SPSR_und
ARM720T CORE CPU MANUAL