Scan Timing; Figure 9-10 Scan Timing; Table 9-6 Scan Chain 1 Cells - Epson ARM720T Core Cpu Manual

During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36 specify the
address of the EmbeddedICE-RT register to be accessed.
During UPDATE-DR, this register is either read or written depending on the value of bit 37
(0 = read, 1 = write). See Figure 9-12 on page 9-34 for more details.
9.15

Scan timing

Figure 9-10 provides general scan timing information.
9.15.1 Scan chain 1 cells
The ARM720T processor provides data for scan chain 1 cells as shown in Table 9-6.
ARM720T CORE CPU MANUAL
HCLK
DBGTCKEN
t
istcken
DBGTMS
DBGTDI
t
istctl
DBGTDO
t
ovtdo

Figure 9-10 Scan timing

Table 9-6 Scan chain 1 cells

Number Signal
1 DATA[0]
2 DATA[1]
3 DATA[2]
4 DATA[3]
5 DATA[4]
6 DATA[5]
7 DATA[6]
8 DATA[7]
9 DATA[8]
10 DATA[9]
11 DATA[10]
12 DATA[11]
13 DATA[12]
14 DATA[13]
EPSON
9: Debugging Your System
t
ihtcken
t
ihtctl
t
ohtdo
Type
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
9-25