Core Memory - GE PAC 4020 System Manual

CORE MEMORY
General Characteristics and Operation
A coincident-current, three-wire magnetic core
memory system is used in the GE/PAC 4020
computer, up to a maximum of 32, 768 words.
Memory full- cycle time for the GE/PAC 4020
computer is 1.6 microseconds. The memory unit
contains its own timing and control to enable external
device controllers to share the core memory with
the arithmetic unit, thereby reducing overall proc-
essing time.
Each word in the core memory contains 24 bits
plus a parity bit. The parity circuitry generates an
odd parity on the write cycle and checks on the read
cycle for an odd total of 11 1's
11
•
The core word is
restored as read, whether or not a parity error
occurs.
Since 14 bits of each instruction are used for
memory addressing, one instruction has direct
access to 16,384 core locations and access to any of
32, 768 locations by indexing or indirect addressing.
The numerous instructions that do not address
memory use this field for microcoded elaborations
on their basic operation code, device and channel
selection, length of shift, or constants. This last
use provides a form of "immediate mode" operation
that saves both time and memory.
Memory Multiplexer
This device switches the core memory between
the arithmetic unit and three channels to external
controllers. The arithmetic unit is given lowest
priority because it can always wait for access
if
necessary. The external controllers drive high
data-rate devices such as bulk memories, data links
to other computers, data acquisition for telemetering
systems, and high-speed peripherals. For high-
speed peripherals, up to eight controllers can share
a single channel. Each can operate up to four de-
vices, one at a time.
The memory multiplexer operates on a true
cycle-stealing basis. Once any of the controllers
has made several accesses to core to load its control
words, it makes only one access (1.6 us) for each
succeeding operation. Even while cycles are being
stolen in this manner, the arithmetic unit will con-
tinue to execute its current instruction, stopping only
when it needs another access to core that cannot be
granted at that instant.
Using these three cycle-stealing channels, the
GE/PAC 4020 computer can communicate with a
large number of high data-rate devices in the most
efficient possible manner.
Dedicated Addresses
The following dedicated memory locations are
typical of the GE/PAC 4020 computer,
if
the named
function is provided. Also, all are addressable and
usable with any GE/PAC command.
OCTAL
00
01}
07
10
11 }
17
20
21
22
23
24
25
26
27
30
31 }
37
40 }
77
100}
177
200}
377
(variable)
FUNCTION
Primary bulk storage pointer word
Index location words
Q location word
Additional bulk storage pointer words
Memory protect error exit location
(SPB)
Memory protect, saved I-register
word
Not dedicated
II II
API stall alarm error exit location
Not dedicated
II II
II II
II II
Common peripheral pointer words
Quasi instruction branch vectors
Memory protect status words
8 to 128 automatic program interrupt
response locations. They may
contain:
(a) Transfers to driver programs
(SPB, BRU)
(b) Memory decrement and test
(DMT) for timing, counting
(c) Table I/O (TIM/TOM) control
words for input-output
(d) No operation (NOP)
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