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For timing, the "event" counted is the passage
of one cycle on the a-c power line - 16.67 ms on a
60-Hz system.
When the
DMT
is used as a program loop
counter, the interrupt system is not involved.
Instead, the
DMT
resets the test flip-flop when the
count goes from zero to minus one. Advantages of
using the
DMT
with the index locations for this
purpose include speed and the fact that the X lo-
cations
are
saved automatically in the event that the
program is interrupted or over-written.
Subroutine linkage
A subroutine consists of a series of instructions
to perform
a
given function required several times
by one program or by several programs.
Relevant
instructions include save place and
branch (SPB) for subroutine entry and
load
place and
restore (LPR) for return to the calling program.
In
addition to the contents of
"P",
these two in-
structions
also
save and restore the contents of four
important control flip-flops, shown in Figure
3.
The SPB stores this information in index lo-
cation one and inhibits interrupts for
one
succeeding
instruction. That
instruction
- the first of the sub-
routine
-
should store Xl in any other memory
lo-
cation. Then the
LPR
can refer to that location in
exiting from the subroutine.
23
22
21
20
19
18
14
13
0
Xl
0
zero
(P)
+
1
~~
~
TMFF
Statu'
TSTF Status
PAIF
Status
OVRF Status
Figure 3
Storing, Reloading the Control Flip-lops
logical Variables
Process control programs spend much of their
time performing logical functions.
The GE/PAC
4020 computer's capabilities include hardware to
.
manipulate individual bits in a word (bit logic),
COUllt-..·
various configurations of ones and zeroes (a form of
partial word logic) and perform four full-word logi-
cal instructions (AND,
OR, Exclusive OR,
and
Complement).
Many of these capabilities are
carried into the GE/PAC Process FORTRAN lan-
guage; all
are
reflected in PAL.
12
Thus, rather than wasting an entire word to
store each logical variable, the GE/PAC 4020
computer can pack 24 into each word, with no addi-
tional running time or programming effort.
Operate on Memory
Inverse to memory operations are carried out by
the
operate
on memory (OOM) quasi, which causes
the memory location addressed by the
QOM
to act as
the A register for the instruction immediately fol-
lowing
the
OOM.
While this feature will not save
running time, it will save memory and enhances
compatibility between the
GE/
PAC 4020 computer
and the earlier GE/PAC 4050, 4050-11 and 4060 ma-
chines, which
implement QOM
as a wired instruction.
Execute
Operations involving
double-indexing, indexing
of otherwise non-indexable instructions, and exe-
cution of commands manufactured by a program are
implemented
in
the GE/PAC 4020 computer by the
execute (XEC)
instruction.
XEC fetches an instruc-
tion from the address given
in
its operand address
field, executes
it,
then transfers control to the in-
struction following the XEC, not the instruction fol-
lowing the object instruction.
Automatic Program Interrupt (API)
This feature saves central processor time, per-
mits faster response to critical external conditions,
operates
1/
0
devices and subsystems at full-rated
speeds without special attention from the system's
programs, and helps the software be certain that
programs are
run
in the desired order of priority as
time passes
and
system conditions change.
Each level of interrupt can recognize and retain
either a momentary signal or a change-of-level sig-
nal. When the
level
is "permitted", program control
will be transferred to a location
unique
for each
level. What happens next
depends
on which instruc-
tion is stored at that location.
The
most frequently
used response commands are:
Save Place and
Branch
(SPB). When a program
is to run as a consequence of the interrupt, this in-
struction stores the P register and control flip-flop
states
of
the running program and enters the re·-
sponse'
program (if it is always in core) or the real-
time executive portion of RTOS
(if
the program may
not be in core).
It
is the responsibility of the re-
sponse program to save any registers it uses or
disturbs
and
to reload them before returning to the
interrupted program.
No Operation (NOP). This instruction is exe-
cuted, but does nothing, after which control is re-
turned to the interrupted program. Storing a NOP in
its API response address is the way to inhibit
an
individual interrupt.
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