Arithmetic Unit - GE PAC 4020 System Manual

ARITHMETIC UNIT
Commands
Maior Types
The GE/PAC 4020 computer accepts two types
of commands, wired and quasi. The first is exe-
cuted without further references to memory, except
for operands; the second causes an automatic entry
and return from a subroutine. This feature saves
programming effort, bulk memory and running time,
since it allows the GE/PAC 4020 central processor
to have a larger and richer command repertoire, to
be essentially program-compatible with the earlier
GE/PAC 4000 computers, and to offer the pro-
grammer such powerful features as circular list
processing and floating-point arithmetic.
The total amount of core required for the entire
GE/PAC 4020 quasi package is approximately 700
words, which includes floating-point arithmetic.
This block of words is included in the 5-6,000 words
generally considered as RTOS 's core requirement.
The GE/PAC 4020 computer's command reper-
toire consists of 112 commands - 92 wired and 20
quasi's. There are 37 of these which reference
memory - 21 wired and 16 quasi's - and 60 which
represent unique and useful microcoded variations
of three of the GE/PAC 4020 computer's 44 primary
operation codes. Of the unused operation codes,
three - 75, 76 and 77 - will cause quasi operation
and can be used for special system instructions or
macroinstructions.
Formats
Instructions
Although the PAL Assembler takes care of
assembling operation codes, addresses and param-
eters into the following formats, it is occasionally
desirable to know them when debugging.
In all the formats, bits 23-18 are either the sole
operation code or the primary one. Bits 17 -15
specify the index location (if any) whose contents will
be added to bits 13-0 of the instruction before exe-
cution. While the primary use of this feature is
automatic address modification of full operand in-
structions, it will also produce the stated result when
used with other types of instructions.
Bits 14-0 vary in significance depending on the
instruction type.
The GE/PAC 4020 central processor's full
operand mode references memory either directly or
relative to the instruction's location, depending on
whether bit 14 is a zero or a one. The GE/PAC 4020
computer, like the rest of the GE/PAC 4000 series,
uses relative addressing for locations within a
program and direct addressing for fixed locations
outside it. Then, whenever the Real-Time Operating
System wants to bring a program from bulk memory
into core and run it, RTOS only needs to find an area
large enough without regard to its starting address,
saving both running time and core. Since the inter-
nal memory references are relative to wherever the
program happens to be, the program will still run
correctly. This feature, called "dynamic relocata-
bility", allows true multiprogramming.
The relative address may be positive or nega-
tive, as shown by bit 13. If bit 13 is a one, bits 12-0
contain the two's complement of the relative address.
Certain instructions, such as add constant to A
(AKA) use the full operand format but carry their
operands with them, in bits 13-0. A form of "imme-
diate mode" addressing, this saves considerable
memory and time when it is usable.
The second major format, called GEN 1, covers
commands used for bit manipulation of tne "A" reg-
ister. Bits 14-5 are microcoded elaborations on the
basic operation code for this format, 05, and bits
4-0 specify the particular bit position desired,
counting down from left to right, or specify the
length of shift. GEN 1 operations include right
shifts, masking, testing, and counting.
GEN 2, distinguished from GEN 1 by its oper-
ation code, 25, is used for I/O operations involving
the "A" register channels. Bits 14-12 are micro-
coding; bits 11-0 contain a device number. One
instruction selects the device and transfers the data
to or from it. A GE/PAC 4020 computer could
address up to 2048 devices, if necessary.
GEN 3, 45, handles left shifts of A and left or
right shifts of A and
Q
together. Bits 12-5 are
microcoded; bits 4-0 specify the length of shift,
0-3110 positions.
The GE/PAC 4020 computer offers the two
formats below for fixed-point arithmetic. The
double-word format is seldom necessary and is used
mainly for large accumulations.
Multiply develops a 46-bit plus sign product
from two 23-bit plus sign factors, and divide de-
velops a 23-bit plus sign quotient and a 23-bit plus
sign remainder from a 46-bit plus sign dividend and
a 23-bit plus sign divisor.
The fixed-point formats represent negative
numbers in two's complement form. The double-
word format ignores the second word's sign bit and
uses the sign bit of the first word for the entire
number.
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