Timing Generation - HP 8112A Operating, Programming And Servicing Manual

Figure 10.3-l. Timing IC block diagram
Refer to Figure 10.3-l and Figure 10.3-6. The timing IC has an input
store containing 8 control bits which control the mode of the IC:
Table 10.3-2. IC Digital Control Signals
Name
1 0 C O N T R O L
ENABLE
1 1 G A T E / T R I G
1 2 T R I G P O S
1 3 T R I G N E G
1 4 T I M E / R A T E
1 5 M O D E
1 6 R A N G E C
1 7 R A N G E B
1 8 R A N G E A

Timing Generation

The main timing element of the IC is a voltage controlled oscillator
(VCO) which has two ranges of operation in each of the two
operating modes (see TIME and RATE below). These two basic
ranges, time and frequency, are further divided if necessary by
switching divider circuits (6 x decade counters) into operation under
control of the range setting.
positive
WS3 A TTL edge on this pin latches all
the digital control signals into the input
store.
LD7 Selects trigger or gate
LD6 Positive trigger
LD5 Negative trigger
LD4 Selects TIME or RATE mode
LD3 Always 0 in this application
LD2 Range selection, refer to Table 10.3-3
L D O
Servicing the Timing and 10.3-3
Function
Slope Generators