Epson S1C17624 Technical Manual page 73

7 ClOCK GeneRaTOR (ClG)
D1 FOuThe: FOuTh Output enable Bit
Enables or disables FOUTH clock (divided HSCLK clock) external output.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
Setting FOUTHE to 1 outputs the FOUTH clock from the FOUTH pin. Setting it to 0 stops the output.
D0 FOuT1e: FOuT1 Output enable Bit
Enables or disables FOUT1 clock (OSC1 clock) external output.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
Setting FOUT1E to 1 outputs the FOUT1 clock from the FOUT1 pin. Setting it to 0 stops the output.
PClK Control Register (ClG_PClK)
Register name address Bit
PClK Control 0x5080 D7–2 –
Register
(8 bits) D1–0 PCKen[1:0] PCLK enable
(ClG_PClK)
D[7:2] Reserved
D[1:0] PCKen[1:0]: PClK enable Bits
Enables or disables clock (PCLK) supply to the internal peripheral modules.
Also set PRUN/PSC_CTL register.
Peripheral modules that use PCLK
• 16-bit timer (T16)
• 8-bit timer (T8F)
• UART
• SPI
• I C master (I2CM)
2
• I 2 C slave (I2CS)
• 16-bit PWM timer (T16E)
• I/O port (P)
• MISC register (MISC)
• Power generator (VD1)
• Supply voltage detector (SVD)
• IR remote controller (REMC)
• A/D converter (ADC10)
• Interrupt controller (ITC)
7-14
Table 7. 9.5 FOUTH clock (HSCLK Division Ratio) Selection
FOuThD[1:0]
0x3
0x2
0x1
0x0
name Function
reserved
Table 7. 9.6 PCLK Control
PCKen[1:0]
0x3
0x2
0x1
0x0
Seiko epson Corporation
Division ratio
Reserved
1/4
1/2
1/1
Setting
–
PCKEN[1:0] PCLK supply
0x3
0x2 Not allowed
0x1 Not allowed
0x0
PRun PClK supply
1 Enabled (on)
*
Setting prohibited
*
Setting prohibited
0 Disabled (off)
(Default: PCKEN[1:0] = 0x3, PRUN = 0)
S1C17624/604/622/602/621 TeChniCal Manual
(Default: 0x0)
init. R/W Remarks
– – 0 when being read.
0x3 R/W
Enable
Disable