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Left justify mode (STMD = 1) (MSB)
Right justify mode (STMD = 0)
This register is a read-only, so writing to this register is ignored.
a/D Trigger/Channel Select Register (aDC10_TRG)
Register name address
Bit
a/D Trigger/
0x5382
D15–14 –
Channel Select
(16 bits)
D13–11 aDCe[2:0] End channel select
Register
D10–8 aDCS[2:0] Start channel select
(aDC10_TRG)
D7
D6
D5–4 aDTS[1:0]
D3
D2–0 aDST[2:0]
D[15:14] Reserved
D[13:11] aDCe[2:0]: end Channel Select Bits
Sets the conversion end channel with a channel number from 0 to 7. (Default: 0x0 = AIN0)
Analog inputs can be A/D-converted continuously from the channel set by ADCS[2:0] to the channel set
by ADCE[2:0] in one A/D conversion. If only one channel is to be A/D converted, set the same channel
number in both ADCS[2:0] and ADCE[2:0].
Table 24.
D[10:8]
aDCS[2:0]: Start Channel Select Bits
Sets the conversion start channel with a channel number from 0 to 7. (Default: 0x0 = AIN0)
D7
STMD: Conversion Result Storing Mode Bit
Selects the data alignment when the conversion results are loaded into ADD[15:0].
1 (R/W): Left justify mode (10-bit conversion results → ADD[15:6], ADD[5:0] = 0)
0 (R/W): Right justify mode (10-bit conversion results → ADD[9:0], ADD[15:10] = 0) (default)
D6
aDMS: Conversion Mode Select Bit
Selects an A/D conversion mode.
1 (R/W): Continuous conversion mode
0 (R/W): One-time conversion mode (default)
Writing 1 to ADMS sets the A/D converter to continuous conversion mode. In this mode, A/D conver-
sions in the range of the channels selected by ADCS[2:0] and ADCE[2:0] are executed continuously
until stopped with software.
S1C17624/604/622/602/621 TeChniCal Manual
ADD bit
15
...
0
...
Figure 24.
6.1 Conversion Data Alignment
name
Function
reserved
STMD
Conversion result storing mode
aDMS
Conversion mode select
Conversion trigger select
–
reserved
Sampling time setting
6.2 Relationship between ADCS/ADCE and Input Channels
aDCS[2:0]/aDCe[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
10
9
...
10-bit conversion results
0
(MSB)
10-bit conversion results
Setting
–
0x0 to 0x7
0x0 to 0x7
1 ADD[15:6]
0 ADD[9:0]
1 Continuous 0 Single
ADTS[1:0]
0x3
#ADTRG pin
0x2
0x1
0x0
–
ADST[2:0]
Sampling time 0x7 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Channel selected
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
24 a/D COnVeRTeR (aDC10)
6
5
...
(LSB)
0
...
init. R/W
Remarks
–
–
0 when being read.
0x0 R/W
0x0 R/W
0
R/W
0
R/W
Trigger
0x0 R/W
reserved
T16 Ch.0
Software
–
–
0 when being read.
9 cycles
8 cycles
7 cycles
6 cycles
5 cycles
4 cycles
3 cycles
2 cycles
(Default: 0x0)
0
0
(LSB)
24-9
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