Epson S1C17624 Technical Manual page 338

aPPenDiX a liST OF i/O ReGiSTeRS
Register name address Bit
P0 Port Schmitt 0x5204 D7–0 P0SM[7:0]
Trigger Control
(8 bits)
Register
(P0_SM)
P0 Port 0x5205 D7–0 P0ie[7:0]
interrupt Mask
(8 bits)
Register
(P0_iMSK)
P0 Port 0x5206 D7–0 P0eDGe[7:0] P0[7:0] port interrupt edge select
interrupt edge
(8 bits)
Select Register
(P0_eDGe)
P0 Port 0x5207 D7–0 P0iF[7:0]
interrupt Flag (8 bits)
Register
(P0_iFlG)
P0 Port 0x5208 D7
Chattering (8 bits) D6–4 P0CF2[2:0] P0[7:4] chattering filter time
Filter Control
Register
(P0_ChaT)
D3
D2–0 P0CF1[2:0] P0[3:0] chattering filter time
P0 Port Key- 0x5209 D7–2 –
entry Reset (8 bits)
D1–0 P0KRST[1:0] P0 port key-entry reset
Configuration
Register
(P0_KRST)
P0 Port input 0x520a D7–0 P0ien[7:0] P0[7:0] port input enable
enable Register (8 bits)
(P0_ien)
P1 Port input 0x5210 D7–0 P1in[7:0]
Data Register
(8 bits)
(P1_in)
P1 Port Output 0x5211 D7–0 P1OuT[7:0] P1[7:0] port output data
Data Register
(8 bits)
(P1_OuT)
P1 Port 0x5212 D7–0 P1Oen[7:0] P1[7:0] port output enable
Output enable
(8 bits)
Register
(P1_Oen)
P1 Port Pull-up 0x5213 D7–0 P1Pu[7:0]
Control Register
(8 bits)
(P1_Pu)
P1 Port Schmitt 0x5214 D7–6 P1SM[7:6]
Trigger Control
(8 bits)
D5–0 P1SM[5:0]
Register
(P1_SM)
P1 Port 0x5215 D7–0 P1ie[7:0]
interrupt Mask (8 bits)
Register
(P1_iMSK)
P1 Port 0x5216 D7–0 P1eDGe[7:0] P1[7:0] port interrupt edge select
interrupt edge
(8 bits)
Select Register
(P1_eDGe)
P1 Port 0x5217 D7–0 P1iF[7:0]
interrupt Flag
(8 bits)
Register
(P1_iFlG)
aP-a-16
name Function
P0[7:0] port Schmitt trigger input
enable
P0[7:0] port interrupt enable
P0[7:0] port interrupt flag
– reserved
–
reserved
reserved
configuration
P1[7:0] port input data
P1[7:0] port pull-up enable
P1[7:6] port Schmitt trigger input
enable
P1[5:0] port Schmitt trigger input
enable
P1[7:0] port interrupt enable
P1[7:0] port interrupt flag
Seiko epson Corporation
Setting init. R/W
1 Enable 0 Disable
(Schmitt) (CMOS)
1 Enable 0 Disable
1 Falling edge 0 Rising edge
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
–
P0CF2[2:0] Filter time
0x7 16384/f 0x0 R/W
PCLK
0x6 8192/f
PCLK
0x5 4096/f
PCLK
0x4 2048/f
PCLK
0x3 1024/f
PCLK
0x2 512/f
PCLK
0x1 256/f
PCLK
0x0 None
–
P0CF1[2:0] Filter time 0x0 R/W
0x7 16384/f
PCLK
0x6 8192/f
PCLK
0x5 4096/f
PCLK
0x4 2048/f
PCLK
0x3 1024/f
PCLK
0x2 512/f
PCLK
0x1 256/f
PCLK
0x0 None
–
P0KRST[1:0] Configuration 0x0 R/W
0x3 P0[3:0] = 0
0x2 P0[2:0] = 0
0x1 P0[1:0] = 0
0x0 Disable
1 Enable 0 Disable
(0xff)
1 1 (H) 0 0 (L)
1 1 (H) 0 0 (L)
1 Enable 0 Disable
1 Enable 0 Disable
(0xff)
1 Enable 0 –
(Schmitt)
1 Enable 0 Disable
(Schmitt) (CMOS)
1 Enable 0 Disable
1 Falling edge 0 Rising edge
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
1 R/W
0 R/W
0 R/W
0 R/W Reset by writing 1.
– – 0 when being read.
0 R/W
– – 0 when being read.
– – 0 when being read.
1 R/W
×
R
0 R/W
0 R/W
1 R/W
1 R Always enabled
1 R/W
0 R/W
0 R/W
0 R/W Reset by writing 1.