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This selector circuit which is controlled
b y
the CPU
(
s t o r a g e
r e g i s t e r
#
3 7 ) will make the
final determination of which time
code source
( LTC
, *
p s e u d o T C
,
or
VITC ) is to be routed
t o
the CPU
board time code reader circuit
.
* :
For
m o r e
information
c o n c e r n i n g
the Pseudo T C
s i g n a l
,
refer to t h e
VVT board
circuit
d e s c r i p t i o n at
the end
of this section
.
S i n c e
the
e x a m p l e b e i n g
discussed will be
u s i n g
the VITC
p o r t
,
s t o r a g e r e g i s t e r
#
3 7 is set to
a
value of 1 and the
VITC s i g n a l
i s
o u t p u t
from the
VVT board
a s
the VSR
( Video
S y n c
Reference ) O U T
s i g n a l
.
This
s i g n a l
is
in
a longitudinal
TTL
format and o u t p u t from the
VVT board via
p i n 8 of
CNJ
-
481
.
T h e selector circuit
o n
the
VVT board
is d i r e c t l y controlled
b y
the MODE A and MODE
B command lines
.
These dedicated
command lines
a r e i n t e r p r e t e d
from the data bus of the CPU
b y
the
8279
(
P r o g r a m m a b l e K e y b o a r d
/ D i s p l a y Interface
,
IC 3 A )
o n
the CNX board
.
T h e information stored in the
r e g i s t e r
#
3 7
mentioned earlier
,
is sent from the CPU board
(
via the data
bus ) to t h e CNX board
.
Hence
,
the 8279 o n the CNX board
decodes the MODE A and MODE
B
commands and routes them via
p i n s
9 and
10
r e s p e c t i v e l y
of CNJ
-
456 ( o n the CNX board )
.
T h e VSR O U T
s i g n a l
(
a s
mentioned earlier
i n
this section ) is
i n p u t
to t h e CNX board ( from the
VVT board )
at p i n 8 of
CNJ
-
456
.
From the
c o n n e c t o r
,
the VSR O U T
s i g n a l
is
TTL
buffered and
o u t p u t to
the
LNT
board via
p i n
30
of CNJ
-
450
a s
the
EXT T C RX
signal
.
The LNT board receives this
signal at
p i n
30 of
CNJ
-
440 and
s i m p l y connects
this
input d i r e c t l y to
the CPU interface connector CNJ
-
441 (
p i n 3 7
)
.
U p o n entering
the CPU board at
p i n 3 7
of CNJ
-
421
,
the
EXT T C
RX
s i g n a l
is buffered and routed
t o the time code
r e c o v e r y
circuit and the Serial Communications Controller ( SCC ) IC 24
.
T h e
t i m e
code
r e c o v e r y
circuit is a d j u s t e d for
o p t i m u m d u t y
c y c l e
(
a s p r e s c r i b e d
in Section 6 of this manual )
,
uses the timing s i g n a l d e v e l o p e d
b y
the time code
r e c o v e r y
circuit to interface the
EXT T C RX
s i g n a l
to the
Z - 8002
p a r a l l e l
data bus
.
T h e S C C
4
-
16
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