2.9 Reset
Logic is provided on the DSP56F807 to generate a clean Power-On RESET signal.
Additional, reset logic is provided to support the RESET signals from the JTAG
connector, the Parallel JTAG Interface and the user RESET push-button; refer to
Figure
2-7.
+3.3V
RESET
PUSHBUTTON
MANUAL RESET
RESET
P_RESET
Figure 2-7. Schematic Diagram of the RESET Interface
2-12
DSP56F807EVM Hardware User's Manual