Motorola Digital DNA DSP56F807 Hardware User Manual page 69

Evaluation module
Table of Contents

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A
4
P O R T _ I DENT
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
3
2 3
2 4
2 5
2
R 7 5
P_RESET
5.1K
R 7 7
47K
1
A
Figure A-16. PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
B
Parallel JTAG Interface
P1
1
PORT_RESET
2
PORT_TMS
3
P O RT_TCK
4
P O R T _TDI
5
/ P O RT_TRST
6
P O R T_DE
7
8
9
P O R T _ VCC
1 0
P O RT_TDO
1 1
1 2
P O R T _ C O NNECT
1 3
DB25M
+3.3V
/ J _ R E SET
R 7 3
5.1K
/ P O R
/ J _ R E SET
Q1
2 N 2222A
/J_TRST
B
C
R 6 4
270
R 6 5
270
R 6 6
270
R 6 7
270
R 6 8
270
T20
+3.3V
R 7 0
5 1 O h m
R 7 1
J G 4
5 1 O h m
On-Board
Host Target Interface
Disable
U 1 8A
U 1 8B
1
4
3
6
/ R E S ET
2
5
74AC00
7 4 AC00
U 1 8 C
U 1 8 D
9
1 2
8
1 1
/TRST
1 0
1 3
74AC00
7 4 AC00
+3.3V
R 7 6
T D O
47K
Title
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
R 7 4
/J_TRST
Document
Size
Number
47K
B
Date:
C
D
U 9
P_RESET
2
1 8
1 A 1
1 Y 1
TMS
4
1 6
1 A 2
1 Y 2
TCK
6
1 4
1 A 3
1 Y 3
TDI
8
1 2
1 A 4
1 Y 4
/J_TRST
1 1
9
2 A 1
2 Y 1
T D O
7
1 3
2 Y 2
2 A 2
5
1 5
+3.3V
2 Y 3
2 A 3
R 6 9
3
1 7
1
2 Y 4
2 A 4
5.1K
2 0
V C C
1
1 G
1 9
1 0
2 G
G N D
R 7 2
MC74LCX244D W
5.1K
+3.3V
J 3
/J_TRST
1 3
1 4
1 1
1 2
/ J _ R E SET
9
1 0
7
8
KEY
T C K
5
6
T D O
3
4
TDI
1
2
JTAG Connector
DSP Standard Products Division
(480) 413-5090
63A10516S
Designer:
Tuesday, December 05, 2000
DSPD Design
D
E
4
3
2
TMS
2100 East Elliot Road
Tempe, Arizona 85284
1
FAX: (480) 413-2510
Rev.
1.0
Sheet
of
16
18
E

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