Hitachi Hidic EH-150 Applications Manual page 71

Preliminary Rev.03
Module Status Register (MDSR)
Bit
+0
Bit 15-8: Reserved
These bits are reserved bits. Usually "0" are set.
Bit 7: Fatal error bit (FAE)
This bit shows that fatal error occurs in the firmware of this module (TCP/IP, UDP/IP protocol). In case that this bit
is "1" The reset operation is required with this module. (by reset button or FUN201)
Bit7: FAE
0
1
Bit 6: Operation mode bit (OPM)
The condition of the bit 1 of the DIP-switch is reflected on this bit.
Bit6: OPM
0
1
Bit 5: SUM Error bit (SME)
The result of the sum check of FALSH memory having system program (Firmware).
Bit5: SME
0
1
Bit 4: Ethernet information configuration error bit (EIE)
Illegal Ethernet information is set. In the case of this bit set "1", I.ERR LED turns on.
Bit4: EIE
0
1
Bit 3: Existence response bit (AVR)
The response of the Existence confirmation is shown here. The data (IAV bit of control register) will be reflected
here.
Bit3: AVR
0
1
Bit 2: Automatic Sending/Receiving enable bit (ATR)
This bit shows the current specified status of Automatic Sending/Receiving function is disable or enable.
Bit2: ATR
0
1
Bit 1: I.ERR LED lighting condition bit (IERR)
This bit shows the current condition of I.ERR LED.
Bit1: IERR
0
1
Bit 0: ERR LED lighting condition bit (ERR)
This bit shows the current condition of ERR LED.
Bit0: ERR
0
1
The contents of this manual might be changed without notice.
15 14 13 12 11
- - - - -
There is no error.
There is fatal error in this module.
Normal operation mode
Ethernet information configuration (set-up) mode.
There is no error.
The sum error is detected. (FLASH memory may be damaged.)
There is no error.
The illegal Ethernet information configuration (set-up) is detected.
The data set in Existence confirmation Request bit (IAV) of Control area are reflected.
Automatic Sending/Receiving function is disable.
Automatic Sending/Receiving function is enable.
I.ERR LED is turned off.
I.ERR LED is turned on.
ERR LED is turned off.
ERR LED is turned on.
10 9 8 7 6
- - - FAE OPM SME EIE AVR ATR IERR ERR
Description
Description
Description
Description
Description
Description
Description
Description
8-2
Chapter 8 Register Structure
5 4 3 2 1 0