Hitachi Hidic EH-150 Applications Manual page 66

Preliminary Rev.03
Cycle time
Received data
Data refresh
Data in CPU
Time chart for connection 2 is shown as Fig. 7.3.2.4.
Register name
EXRR.ARP2 = 1
RDCR.ARE2
C2CSR.RXC2
(1). When data should be refreshed, set 1 to "Ready to transmit" bit (RECR.ASE1).
---------------------------------------------------------------------------------------------------------------Request to refresh data
(2). EH-ETH receives the request and sends designated data to CPU. After the sending completed, EH-ETH sets 1 to
"Receiving completed" bit (C2CSR.RXC2).
------------------------------------------------------------------------------------------------------------------ Receiving completed
(3). Confirm sending completed by C2CSR.RXC2=1, and cancel the "Ready to receive" bit (RDCR.ASE2). If data
should be refreshed continuously, the cancellation is not necessary.
------------------------------------------------------------------------------------------------ Cancellation of a request to refresh
(4). EH-ETH receives the request to cancel, and clear the "Receiving completion" bit (C2CSR.RXC2).
------------------------------------------------------------------------------------------------------ Clear receiving completion bit
- Description in this manual might be modified without notice.
A
0
Fig. 7.3.2.3 Time chart ("Optional receiving" enabled)
"Optional receiving" always enabled.
(1)
: By user, : By EH-ETH
Fig. 7.3.2.4 Procedure of Optional receiving
7-19
Chapter 7 Automatic data transmission
B C D
B
(4)
(2) (3)
E F
D E