Toshiba TLCS-90 Series Data Book page 314

TOSHIBA TMP90C840
Q)
Baud-rate generator
The baud-rate generator comprises a circuit that generates a clock
pulse to determine the transfer speed for transmission/receiving in
the asynchronous communication (UART) mode.
The input clock to the baud-rate generator ~T4, ~T16, ~T64 or ~T256 is
generated by the 9-bit prescaler. One of these input clocks is
selected by the timer/serial channel control register TRUN7, 6
(BRATE).
Also,. either no frequency division or 1/2 division can be selected by
the serial channel mode register SCMOD1, 0 (SC1, 0).
Tab Ie 3.8 (1) shows the baud-rate wh'en fc
=
9.8304 MHz.
Table 3.8 (1) Baud Rate Selection
1
BRATE
1
Input clock
1
No division(SC1,0=0l)
1
1/2 division(SCl,O=ll)
1
1---------1-------------1-----------------------1------------------------1
1
00
1
¢T256
1
300 bps
1
150 bps
1
1---------1-------------1-----------------------1------------------------1
1
01
1
¢T64
1
1200 bps
1
600 bps
1
1---------1-------------1"-----------------------1------------------------1
1
10
1
¢T16
1
4800 bps \ 2400 bps
1
\---------\-------------\-----------------------\------------------------1
\ 11 \ ¢T4 \ 19200 bps \ 9600 bps \
@fc = 9.8304 MHz
GO
Serial clock generating circuit
This circuit generates the basic clock for transmitting and receiving
data.
1) In case of I/O interface mode
It generates a clock at a 1/8 frequency of the system clock (fc).
This clock is output from the SCLK pin (also used as P32/RTS).
2) In case of asynchronous commumication (UART) mode
A basic clock is generated based on the above baud rate generator
clock, the internal clock 01, or the match signal from Timer 2, as
selected by bits 1 and 0 of SCMOD register (SC).
CD
Receiving counter
The receiving counter is a 4-bit binary counter used in the
asynchronous communication (UART) mode and is counted by using SIOCLK.
16 pulses of SIOCLK is used for receiving 1 bit data. The data are
sampled three times at 7th, 8th and 9th pulses and evaluated by the
rule of majority. For example, if data sampled at the 7th, 8th and
9th clock are "1", "0" and "1", the recieved data is evaluated as "1".
The sampled data "0", "0" and "1" is evaluated that the received data
is "0".
~
Receiving control
1) In case of I/O interface mode
The RxD signa 1 is sampled on the rising edge of the shi ft clock
which is output to the SCLK pin.
MPU90-116