GE PACSystems RX7i Cpu Programmer's Reference Manual page 190

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Array Move Example 1
To define the input memory block %R0001 - %R0016 and the
output memory block %R0100 - %R0115, SR is set as %R0001,
DS is set as %R0100, and Length is set to 16.
To copy the five registers %R0003 - %R0007 to the registers
%R0104 - %R0108, N is set to 5, SNX=%R0100 is set to 3 (to
designate the third register, %R0003, of the block starting at
%R0001), and DNX is set to 5 (to designate the fifth register,
%R0104, of the block starting at %R0100).
Array Move Example 2
Using bit memory blocks, the input block starts at SR=%M0009,
the output block starts at %Q0022, and the length of both
blocks is 16 one-bit registers (Length=16).
To copy the seven registers %M0011 - %M0017 to %Q0026 -
%Q0032, N is set to 7, SNX is set to 3 (to designate the third
register, %M0011, of the block starting at %M0009), and DNX is
set to 5 (to designate the fifth register, %Q0026, of the block
starting at %Q0022).
Array Move Example 3
Sixteen (=N) bits that are not byte-aligned are moved from the
two 16-bit registers that start at %R00001 (SR) to the two 16-bit
registers that begin at %R00100 (DS). For the purposes of this
Boolean move, Length is set to 20, because the other 12 bits in
either memory block are not considered.
By setting SNX to 3, N to 16, and DNX to 5, the third (SNX) least
significant bit of %R0001 through the second least significant bit
of %R0002 (for a total of 16 bits=N) are written into the fifth
(DNX) least significant bit of %R0100 through the fourth least
significant bit of %R0101 (for the same total of 16 bits).
GFK-2950C
Chapter 4. Ladder Diagram (LD) Programming
February 2018
175

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