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Figure Number
1-1
KS8910 PHY Transceiver (64-QFP-1414 Package) .........................................................1-1
1-2
Ethernet System Overview Diagram with Emphasis on MDI .............................................1-3
1-3
100/10 Mbps Ethernet Transceiver Block Diagram ...........................................................1-3
2-1
External Signals .................................................................................................................2-2
2-2
KS8910 Pin Assignments ..................................................................................................2-3
3-1
Functional Block Diagram of KS8910 ................................................................................3-1
3-2
100Base-TX Digital Block of KS8910 .................................................................................3-3
3-3
Analog Blocks of KS8910 ..................................................................................................3-5
4-1
100Base-TX Operational Block Diagram of KS8910 .........................................................4-3
4-2
PCS Functional Block Diagram of KS8910 .......................................................................4-4
4-3
4B/5B Encoder (Transmit) State Diagram of KS8910 .......................................................4-7
4-4
5B/4B Decoder (Receive) State Diagram of KS8910 ........................................................4-8
4-5
Linear Feedback Shift Register (LFSR) .............................................................................4-10
4-6
Scrambler Function of KS8910 ..........................................................................................4-10
4-7
Descramble Function of KS8910 .......................................................................................4-11
4-8
Link Monitor State Diagram of KS8910 .............................................................................4-12
4-9
NRZ to NRZI Conversion of KS8910 .................................................................................4-13
5-1
State Diagram of Jabber Control Function ........................................................................5-2
5-2
SQE Function ....................................................................................................................5-3
5-3
State Diagram of Collision Detection Function ..................................................................5-4
5-4
State Diagram of Link Integrity Test Function ...................................................................5-5
6-1
100Mbit/s Data Path Block Diagram of KS8910 ................................................................6-1
6-2
Analog Blocks of KS8910 ..................................................................................................6-2
6-3
Crystal Oscillator Connection ............................................................................................6-3
6-4
Transmit Twister-Pair Driver and Transmit Transformer ...................................................6-5
6-5
Receive Buffer Circuit Configuration .................................................................................6-6
8-1
Clock Frequency Timing Diagram .....................................................................................8-5
8-2
MII-Transmit Clock Tolerance Timing Diagram .................................................................8-5
8-3
MII-Receive Clock Tolerance Timing Diagram ..................................................................8-6
8-4
MII/10Base-T Transmit Timing Diagram ............................................................................8-7
8-5
MII/10Base-T Receive Timing Diagram .............................................................................8-8
8-6
MII/100Base-TX Transmit Timing Diagram .......................................................................8-9
8-7
MII/100Base-TX Receive Timing Diagram ........................................................................8-10
8-8
MII-Management Interface Timing Diagram ......................................................................8-11
8-9
Power On Reset Timming Diagram ...................................................................................8-12
8-10
10Base-T (SQE)Heartbeat Timing Diagram ......................................................................8-13
8-11
10Base-T Jabber Timing Diagram .....................................................................................8-14
8-12
10Base-T Normal Link Pulse Timing Diagram ..................................................................8-15
8-13
Auto-Negotiation and Fast Link Pulse Timing Diagram .....................................................8-16
9-1
KS8910 (64-QFP-1414) Schematic Diagram with KS8920 ...............................................9-1
10-1
KS8910 Package Dimension (64-QFP-1414) Type ...........................................................10-1
x
List of Figures
Title
PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER
Page Number
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