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Preliminary Spec. ver
1.4
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
A differential loop filter is integrated on chip. This loop filter forms a second-order loop. Higher order high frequency
poles are added by on-chip filters. The VCO gain is 140MHz/Volt, and the charge pump current is 20uA. The
recommended components result in a loop bandwidth of 250KHz and a phase margin of 75 degrees.
SIGNAL DECTECTOR
The Signal Detector monitors signal amplitude on cable and inform Digital Block about existence of 100
Rx_code_bit by checking link_status. Threshold of Detect Assertion is 400mVp-p and Detect Deassertion is
300mVp-p.
10MBIT/S TRANSMIT CIRCUITS
The 10Mbit/s Transmit analog block generates the clocks required for data transmission and drives the twisted pair.
An oscillation circuit synthesizes clocks from a 25MHz crystal reference. The 10Base-T Transmit Driver provides
an output capable of driving a transformer-coupled unshielded twisted pair. The Clock generator block, Wave
shaper block and Driver block is combined use with 100Mbit/s Analog Block.
TRANSMIT WAVE SHAPER
The Transmit Wave Shaper takes a manchester encoded bit-stream and converts it into a waveshape that fits the
IEEE 802.3 template. refer to IEEE802.3u
10MBIT/S RECEIVE CIRCUITS
The receive circuits include a receive buffer, an adaptive equalizer, a baseline restore circuit, and receive clock
recovery. The outputs of the analog receive block are data on 10RXD and a recovered clock on 20RXClk. The
presence of a receive signal is signaled as RXSignal Detect. The clock recovery lock detect is signaled on
RXClkLock.
RECEIVER
The 10Base receiver has three function blocks : attenuator, receiver, and squelch generator. The attenuator
receives signal range which is specified in the IEEE802.3 and has DC biased at 1.8V. The attenuator is to ensure
the largest input signal amplitude fill below the 3V power supply before feeding the signal to the receiver.
The receiver detects signals with specification listed in IEEE802.3, and generates output signal for the squelch
generator. The squelch generator output a self-time pulse(typical 300ns or 3bit width) triggered by the rising edge
of the sugnal from the receiver. This pulse signals the valid input data is receiving.
The input voltage at the input should be ±585mV differential. The receive buffer automatically generates its
common mode input reference. This allows operation with AC coupled signals. A voltage division and transmission
100BASE-TX ANALOG BLOCKS
6-7
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