Frequency Detection - GE L90 Instruction Manual

8 THEORY OF OPERATION
f – f1
+
+
+
ϕ ϕ
( 2 – 1)/2
θ θ
( 2 – 1)/2
Figure 8–1: BLOCK DIAGRAM FOR CLOCK SYNCHRONIZATION IN A 2-TERMINAL SYSTEM
The L90 provides sensitive digital current differential protection by computing differential current from current phasors. To
improve sensitivity, the clocks are controlling current sampling are closely synchronized via the ping-pong algorithm. How-
ever, this algorithm assumes the communication channel delay is identical in each direction. If the delays are not the same,
the error between current phasors is equal to half of the transmit-receive time difference. If the error is high enough, the
relay perceives the "apparent" differential current and misoperates.
For applications where the communication channel is not symmetric (for example, SONET ring), the L90 allows the use of
GPS (Global Positioning System) to compensate for the channel delay asymmetry. This feature requires a GPS receiver to
provide a GPS clock signal to the L90 IRIG-B input. With this option there are two clocks as each terminal: a local sampling
clock and a local GPS clock. The sampling clock controls data sampling while the GPS clock provides an accurate, abso-
lute time reference used to measure channel asymmetry. The local sampling clocks are synchronized to each other in
phase and to the power system in frequency. The local GPS clocks are synchronized to GPS time using the externally pro-
vided GPS time signal.
GPS time stamp is included in the transmitted packet along with the sampling clock time stamp. Both sampling clock devia-
tion and channel asymmetry are computed from the four time-stamps. One half of the channel asymmetry is then sub-
tracted from the computed sampling clock deviation. The compensated deviation drives the phase and frequency lock loop
(PFLL) as shown on the diagram above. If GPS time reference is lost, the channel asymmetry compensation is not
enabled, and the relay clock may start to drift and accumulate differential error. In this case, the 87L function has to be
blocked. Refer to Chapter 9: Application of Settings for samples of how to program the relay.
Estimation of frequency deviation is done locally at each relay based on rotation of positive sequence current, or on rotation
of positive sequence voltage, if it is available. The counter clockwise rotation rate is proportional to the difference between
the desired clock frequency and the actual clock frequency. With the peer to peer architecture, there is redundant frequency
tracking, so it is not necessary that all terminals perform frequency detection.
Normally each relay will detect frequency deviation, but if there is no current flowing nor voltage measurement available at
a particular relay, it will not be able to detect frequency deviation. In that case, the frequency deviation input to the loop filter
is set to zero and frequency tracking is still achieved because of phase locking to the other clocks. If frequency detection is
lost at all terminals because there is no current flowing then the clocks continue to operate at the frequency present at the
time of the loss of frequency detection. Tracking will resume as soon as there is current.
GE Multilin
RELAY 1
f System
Frequency
+
_
Compute
Frequency
f1
Deviation
Phase Frequency
Loop Filter
ϕ1
Ping-Pong
Phase
Deviation
GPS
Phase
Deviation
θ
GPS
Clock
L90 Line Differential Relay
RELAY 2
f
+
_
Compute
Frequency
f2
Deviation
Phase Frequency
Loop Filter
ϕ2
Ping-Pong ϕ
time stamps
( 2 – 1)/2
Phase
Deviation
GPS
time stamps ( 2 – 1)/2
Phase
Deviation
θ
GPS
Clock

8.1.9 FREQUENCY DETECTION

8.1 OVERVIEW
f – f2
+
+
+
ϕ
θ θ
831026A1.CDR
8-5
8