Controller Mnemonics - HP 7925D Service Manual

7925
Appendix A
Table A-I. Controller Mnemonics
MNEMONIC SIGNAL
FUNCTION
AlU IMM AlU Immediate
ANYER Any Error
ATN Attention (ground true)
CARRY Carry Bit
CBUSl Control Bus, lower Byte
CBUSU Control Bus, Upper Byte
DAV Data Valid (ground true)
DDB, DDB Differential Data Bus
DIO 1-8 Data Input/Output
DT
Data Test
DTYPE Drive Type
EOI End or Identify (ground true)
EOT End of Transmission
EOW End of Word
ERE External ROM Enable
ALU Clock
Data Input Bus
Data Output Bus
HDREG Head Register
IE
Input Enable
IFC Interface Clear
IFIFO
Input from FIFO
ADBI0-7
ADBO 0-7
AlU ClK
EXADBOE
EXRAREN
Eight-bit bus providing input data for microprocessor.
Eight-bit bus carrying data from microprocessor.
Clock having a 75-percent duty cycle and 276 nanosecond
period that runs ALU chips, Program Status register, and
Output Address decoder.
Allows data byte from microcode word to be used by ALU or
output through ALU.
Flag indicating that an error has been detected by cyclic re.-
dundancy check (CRC) circuit during a read or verify.
Bidirectional HP-IB control signal.
Flag indicating that a one has been moved left from most
significant bit of ALU by a shift or arithmetic operation.
Enables loading output register containing lower byte of cyl-
inder address or offset value.
Enables loading output register containing upper bits of cyl-
inder address or offset or T-bit and select.
Bidirectional HP-IB control line.
Serial data between formatter/separator and read/write
circuitry.
Eight-bit wide HP-IB bidirectional data bus.
Signal from Self-Test output register to formatter/separator
enabling data loopback.
Enables reading of input register containing drive type, rota-
tional position sensing (RPS) enable, sector compare, and
device address.
Bidirectional HP-IB control line.
Flag from DMA handshake logic to microprocessor indicating
that read or write of a sector is complete.
Flag from data path End-of-Word counter indicating that a
byte has been clocked to/from formatter/separator circuitry.
Grounding this line turns off internal PROMS, allowing
external microcode store to be connected to microprocessor
PCA-A2 via connector A2J2.
External AlU Output Data Bus Enable Grounding this line allows output data bus to be driveR from
connector J1 of microprocessor PCA-A2.
External Clear Grounding this line on connector J2 of microprocessor
PCA-A2 resets microprocessor to zero memory location. Sig-
nal action is similar to PON.
External RAR Enable Grounding this line on connector J2 of microprocessor
PCA-A2 allows microcode memory to be addressed via con-
nector J2 of PCA-A2.
Enables loading of Head Register from data output bus.
Enables loading of AlU from bidirectional buffer via input
data bus.
Bidirectional HP-IB control line.
Enables transfer of data from first-in-first-out memory
(FIFO) to AlU.
A-7