Texas Instruments MSPM0G350 Series Instruction Manual page 49

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7.20.1 SPI (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
t PICO output data hold time
HD.CO
Peripheral
t CS lead-time, CS active to clock
CS.LEAD
CS lag time, Last clock to CS
t
CS.LAG
inactive
CS access time, CS active to POCI
t
CS.ACC
data out
CS disable time, CS inactive to
t
CS.DIS
POCI high inpedance
t PICO input data setup time
SU.PI
t PICO input data hold time
HD.PI
t POCI output data valid time
VALID.PO
t POCI output data valid time
VALID.PO
t POCI output data hold time
HD.PO
(1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge
7.20.2 SPI Timing Diagram
CS
(inverted)
t
CS, LEAD
CS
1 / f
SPI
SCLK
(SPO = 0)
t t
SCLK_H/L
SCLK_H/L
SCLK
(SPO = 1)
POCI
t
HD,CO
t t
CS, ACC VALID,CO
PICO
Controller Mode, SPH = 0
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TEST CONDITIONS
(3)
(2)
2.7 < VDD < 3.6V
(2)
1.62 < VDD < 2.7V
(3)
t
CS, LAG
t
SU,CI
t
HD,CI
t
CS, DIS
Figure 7-6. SPI timing diagram - Controller Mode
Product Folder Links: MSPM0G3507 MSPM0G3506 MSPM0G3505
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
31.25
CS
(inverted)
t
CS, LEAD
CS
1 / f
SPI
SCLK
(SPO = 0)
t t
SCLK_H/L SCLK_H/L
SCLK
(SPO = 1)
t
CS, ACC
POCI
PICO
Controller Mode, SPH = 1
MIN TYP MAX UNIT
1 ns
8 ns
1 ns
23 ns
19 ns
7 ns
ns
24 ns
31 ns
12 ns
t
CS, LAG
t
SU,CI
t
HD,CI
t
HD,CO
t
VALID,CO
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t
CS, DIS
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