Texas Instruments MSPM0G350 Series Manual
Texas Instruments MSPM0G350 Series Manual

Texas Instruments MSPM0G350 Series Manual

Automotive mixed-signal microcontrollers with can-fd interface
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MSPM0G350x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface

1 Features

Qualified for automotive applications
Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80 MHz
Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
Memories
– Up to 128KB of flash memory with error
correction code (ECC)
– Up to 32KB of SRAM with hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADCs) with up to
17 external channels
14-bit effective resolution at 250-ksps with
hardware averaging
– One 12-bit 1-MSPS digital-to-analog converter
with integrated output buffer (DAC)
– Two zero-drift zero-crossover chopper op-amps
(OPA)
0.5-µV/°C drift with chopping
Integrated programmable gain stage, up to
32x
– One general-purpose amplifier (GPAMP)
– Three high-speed comparators (COMP) with 8-
bit reference DACs
32-ns propagation delay in high-speed
mode
Support low-power mode operation down to
0.7 µA
– Programmable analog connections between
ADC, OPAs, COMP and DAC
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
– Integrated supply monitor
Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 467 µA at 4 MHz
– STOP: 46 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 80 nA with IO wake-up capability
Intelligent digital peripherals
– 7-channel DMA controller
– Math accelerator supports DIV, SQRT, MAC
and TRIG computations
– Seven timers supports up to 22 PWM channels
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
-M0+ CPU with memory
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
One 16-bit general-purpose timer
One 16-bit general-purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit high-resolution general-purpose
timer
Two 16-bit advanced timers with deadband
support up to 12 PWM channels
– Two window-watchdog timers
– RTC with alarm and calendar mode
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
2
– Two I
C interfaces support up to FM+
(1 Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32 Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
Clock system
– Internal 4- to 32-MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz low-frequency oscillator
(LFOSC) with ±3% accuracy
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
Flexible I/O features
– Up to 60 GPIOs
Two 5-V tolerant IOs
Two high-drive IOs with 20-mA drive
strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 64-pin LQFP
– 48-pin LQFP, VQFN
– 32-pin VQFN
– 28-pin VSSOP
– 24-pin VQFN
Family members (also see
– MSPM0G3505: 32KB flash, 16KB RAM
– MSPM0G3506: 64KB flash, 32KB RAM
SLASF88 – OCTOBER 2023
Device
Comparison)

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Summary of Contents for Texas Instruments MSPM0G350 Series

  • Page 1: Features

    MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 MSPM0G350x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface • One 16-bit general-purpose timer 1 Features • One 16-bit general-purpose timer supports • Qualified for automotive applications • Core • Two 16-bit general-purpose timers support low-power operation in STANDBY mode –...
  • Page 2: Applications

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 3: Functional Block Diagram

    VCORE, NRST PD1, CPU/DMA ACCESS to OPA0 and OPA1, respectively ROSC PD1/PD0, CPU/DMA ACCESS CLK_OUT, FCC_IN PD0, CPU/DMA ACCESS Figure 4-1. MSPM0G350x Functional Block Diagram Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 4: Table Of Contents

    8.3 Power Management Unit (PMU)....... 10.8 Glossary..............78 8.4 Clock Module (CKM)..........54 11 Mechanical, Packaging, and Orderable 8.5 DMA................Information..............8.6 Events............... 12 Revision History ............8.7 Memory..............Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section For more information about the device name, see Section 10.2 24, 32 and 48-pin VQFN packages are available with wettable flanks Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 6: Pin Configuration And Functions

    PA30 PA20 / SWCLK PA29 PB17 / A1_4 PA28 PB18 / A1_5 PB19 / A1_6 PA0 / FCC_IN Figure 6-2. 64-Pin PM (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 7 PA12 / FCC_IN PA4 / LFCLK_IN / LFXOUT PB16 PA5 / HFXIN / FCC_IN PB15 PA6 / HFCLK_IN / HFXOUT Figure 6-3. 48-Pin PT (LQFP) (Top View) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 8 PA4 / LFCLK_IN / LFXOUT PA12 / FCC_IN PA5 / HFXIN / FCC_IN PB16 PA6 / HFCLK_IN / HFXOUT PB15 Thermal pad Figure 6-4. 48-Pin RGZ (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 9 PA4 / LFCLK_IN / LFXOUT PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA11 PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT Figure 6-6. 28-Pin DGS28 (VSSOP) (Top View) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 10 Figure 6-7. 24-Pin RGE (VQFN) (Top View) Note For the full pin configuration and description of the functions for each package option, see Attributes Signal Descriptions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 11: Pin Attributes

    CAN_TX [5] / TIMA0_C3 [6] / FCC_IN [7] Speed UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] / High- PA13 COMP0_IN2- – TIMG0_C1 [5] / CAN_RX [6] / TIMA0_C3N [7] Speed Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 12 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] / – – – Standard TIMA0_C2 [5] UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] / – – – Standard TIMA0_C2N [5] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 13 Standard SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / PB24 A0_5 / COMP1_IN1+ – – Standard TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 14: Signal Descriptions

    ADC1 analog input 4 A1_5 – – – ADC1 analog input 5 A1_6 – – – ADC1 analog input 6 A1_7 ADC1 analog input 7 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 15 Digital low-frequency clock input LFXIN – Input for low-frequency crystal oscillator LFXT LFXOUT Output of low-frequency crystal oscillator LFXT External resistor used for improving oscillator ROSC accuracy Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 16 Serial wire debug data input/output FCC_IN Frequency clock counter input GPAMP_IN+ GPAMP noninverting terminal input General- Purpose GPAMP_IN- GPAMP inverting terminal input Amplifier GPAMP_OUT GPAMP output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 17 – – General-purpose digital I/O PA30 – – – – General-purpose digital I/O General-purpose digital I/O with wake up from PA31 – – – SHUTDOWN Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 18 General-purpose digital I/O PB27 – – – – General-purpose digital I/O I2C0_SCL I2C0 serial clock I2C0_SDA I2C0 serial data I2C1_SCL I2C1 serial clock I2C1_SDA I2C1 serial data Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 19 Power VCORE Regulated core power supply output QFN package exposed thermal pad. TI recommends QFN Pad – – connection to V RTC_OUT RTC clock output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 20 SPI1_SCK Clock signal output – SPI controller mode SPI1_POCI – SPI1 controller in/peripheral out SPI1_PICO SPI1 controller out/peripheral in System NRST Reset input active low Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 21 General purpose timer 7 CCR1 capture input/ TIMG7_C0 compare output General purpose timer 7 CCR1 capture input/ TIMG7_C1 compare output General purpose timer 8 CCR0 capture input/ TIMG8_C0 compare output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 22 Advanced control timer 0 CCR0 compare output TIMA0_C0N (inverting) Advanced control timer 0 CCR1 capture input/ TIMA0_C1 compare output Advanced control timer 0 CCR1 compare output TIMA0_C1N (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 23 Advanced control timer 0 CCR3 compare output TIMA1_C0N – (inverting) Advanced control timer 1 CCR1 capture input/ TIMA1_C1 compare output Advanced control timer 1 CCR1 compare output TIMA1_C1N (inverting) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 24 UART2 transmit data UART2_RX UART2 receive data UART2_CTS – UART2 "clear to send" flow control input UART2_RTS – UART2 "request to send" flow control output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 25 When using VREF+/- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 26: Connections For Unused Pins

    Section 9.1. Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx and PBx" unused pin connection guidelines. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 27: Specifications

    Capacitor connected between VDD and VSS µF (1) (2) Capacitor connected between VCORE and VSS VCORE Ambient temperature, Q version –40 °C Max junction temperature, Q version °C Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 28: Thermal Information

    Junction-to-board thermal resistance 41.3 °C/W θJB VSSOP-28 (DGS28) Ψ Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 41.0 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 29 Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 30: Supply Current Characteristics

    32kHz STOP2 ULPCLK=LFCLK STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, RTC enabled 32kHz µA LFCLK=LFXT, STOPCLKSTBY=1, STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, GPIOA enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 31: Power Supply Sequencing

    Device operating in RUN, SLEEP, or STOP mode. 7.6.2 Power Supply Ramp Figure 7-1 shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 32: Flash Memory Characteristics

    Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 33: Timing Characteristics

    The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 34: Clock Specifications

    The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 35 7.9.4 Low Frequency Crystal/Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Low frequency crystal oscillator (LFXT) LFXT frequency 32768 LFXT Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 36 Manual.Current consumption increases with higher RSEL and start up time is decreases with higher RSEL. The digital clock input (HFCLK_IN) accepts a logic level square wave clock. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 37: Digital Io

    ≤130 °C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 38 VDD ≥ 1.71V, DRV = 0, CL= 20pF HDIO VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 39: Analog Mux Vboost

    Power supply rejection ratio, AC ΔVDD = 0.1 V at 1 kHz Internal reference, V = VREF = 2.5V ADC Wakeup Time Assumes internal reference is active wakeup Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 40 Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with V = VREF+ = VDD and V = VSS = 0V, external 1uF cap on VREF+ pin. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 41: Temperature Sensor

    BUFCONFIG = {0, 1}, No load µA VREF VREF output drive strength Drive strength supported on VREF+ device pin µA Drive VREF short circuit current Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 42: Comparator (Comp)

    Power Mode comp consumption. Vcm = VDD/2, 100mV overdrive, comparator only. µA High Speed Mode Vcm = VDD/2, 100mV overdrive, comparator µA only, Low Power Mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 43: Dac

    Vref = external reference, 4kHz input with 1Msps sampling rate 11.5 bits A low pass filter with 300 Hz to 4 kHz pass band connected at DAC output pin. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 44: Gpamp

    = 10 kHz Input resistance 0.65 kΩ Common mode Input capacitance Differential Open-loop voltage gain, DC = 350 kΩ, 0.3 < Vo < VDD-0.3 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 45: Opa

    GBW = 0x1 µV/°C drift CHOP = 0x1 or 0x2 CHOP = 0x0 Power Supply Rejection Ratio, PSRR Noninverting, unity gain CHOP = 0x1 or 0x2 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 46 GBW = 0x0 = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, OPA settling time µs SETTLE ENABLE = 0x1, Noninverting, unity gain GBW = 0x1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 47: I2C

    SU,STA START Data hold time HD,DAT Data setup time SU,DAT Setup time for STOP 0.26 SU,STO bus free time between a STOP and START condition Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 48: Spi

    2.7 < VDD < 3.6V Controller mode with High speed IO Clock max speed >= 32MHz SPI clock frequency 1.62 < VDD < 3.6V Peripheral mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 49 Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 50: Uart

    UART BITCLK clock frequency(equals UART in Power Domain1 BITCLK baud rate in MBaud) BITCLK clock frequency(equals UART in Power Domain0 BITCLK baud rate in MBaud) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 51: Timx

    51.2 µs LAT256 20MHz 7.24 Emulation and Debug 7.24.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 52: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 53 FULL DRIVE REDUCED DRIVE LOW DRIVE DIS (triggers supported) Core Functions Flash SRAM UART3 SPI0, SPI1 MATHACL Peripherals MCAN0 TIMA0, TIMA1 TIMG6, TIMG7 TIMG1, TIMG12 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 54: Power Management Unit (Pmu)

    For more details, see the PMU chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. 8.4 Clock Module (CKM) The clock module provides the following oscillators: Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 55: Dma

    Generic Subscriber 0 (FSUB_0) SPI1 Publisher 2 Generic Subscriber 1 (FSUB_1) UART3 Publisher 1 AES Publisher 1 UART3 Publisher 2 AES Publisher 2 UART0 Publisher 1 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 56: Events

    Generic event channel 11 selected 1 : 1 Generic event channel 12 selected 1 : 2 (splitter) Generic event channel 13 selected 1 : 2 (splitter) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 57: Memory

    0x41C5.0080 0x41C5.0080 0x41C5.0080 0x41C6.0000 to 0x41C6.0000 to 0x41C6.0000 to FACTORY ECC code 0x41C6.0080 0x41C6.0080 0x41C6.0080 0x6000.0000 to 0x6000.0000 to 0x6000.0000 to Subsystem 0x7FFF.FFFF 0x7FFF.FFFF 0x7FFF.FFFF Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 58 0x40440000 0x2000 0x40442000 0x2000 TRNG 0x40444000 0x2000 SPI0 0x40468000 0x2000 SPI1 0x4046A000 0x2000 UART3 0x40500000 0x2000 CAN-FD 0x40508000 0x8000 ADC0 0x40000000 0x1000 ADC1 0x40002000 0x1000 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 59 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 60: Flash Memory

    Hardware ECC protection (encode and decode) with single bit error correction and double-bit error detection • In-circuit program and erase operations supported across the entire recommended supply range Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 61: Sram

    Up to 17 total external input channels with individual result storage registers • Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, DAC, etc.) • Software selectable reference: Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 62: Temperature Sensor

    Requires a decoupling capacitor placed on VREF+/- pins for proper operation. See VREF specification section for more details For more details, see the VREF chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 63: Comp

    COMP2_IN1- The connection to COMP0/1_IN3+ and DAC_OUT connects using the PA15 pin. When connecting DAC_OUT to COMP0/1_IN3+, avoid using external circuitry on the PA15 pin. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 64: Dac

    OPA1_RTOP GPAMP Output GROUND Table 8-13. OPA1 Input Channel Mapping PSEL P-MUX INPUTS NSEL N-MUX INPUTS MSEL M-MUX INPUTS Open Open Open OPA1_IN0+ OPA1_IN0- OPA1_IN1- Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 65: Gpamp

    AES ready interrupt generation • Available in RUN and SLEEP modes For more details, see the AES chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 66: Crc

    UART3 (Main) Active in Stop and Standby Mode Separate transmit and receive FIFOs Support hardware flow control Support 9-bit configuration Support LIN mode Support DALI Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 67: I2C

    Up to 32 dedicated transmit buffers and 64 dedicated receive buffers Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback...
  • Page 68: Wwdt

    8-bit programmable prescaler to divide the counter clock frequency • Two independent channels for – Output compare – Input capture – PWM output – One-shot mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 69 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved Table 8-17. TIMx Cross Trigger Map (PD0) TSEL.ETSEL Selection TIMG0 TIMG8 TIMG0.TRIG0 TIMG0.TRIG0 TIMG8.TRIG0 TIMG8.TRIG0 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 70 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 71: Device Analog Connections

    Figure 8-1. Device Analog Connection Note Enabling DAC_OUT connects to PA15 therefore it is not recommended to have any external signal on PA15 when using DAC_OUT. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 72: Input/Output Diagrams

    DOUT Peripheral 15 RSTN Driver Logic Unassigned Peripheral 01 Hi-Z Peripheral 15 RSTN PF != 0 PIPU PIPD SHUTDOWN RELEASE Figure 8-2. Superset Input/Output Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 73: Serial Wire Debug Interface

    Please refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for more information. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 74: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 75: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 76: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 77: Tools And Software

    GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain. Arm GCC is supported by Code Composer Studio IDE (CCS). Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 78: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 79: Mechanical, Packaging, And Orderable Information

    12 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 Initial Release Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1...
  • Page 80 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2023 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) XM0G3507QDGS28RQ1 ACTIVE VSSOP 5000 Call TI Call TI -40 to 125 Samples XM0G3507QPTRQ1...
  • Page 81 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
  • Page 82 GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 7 x 7, 0.5 mm pitch Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com...
  • Page 83 PACKAGE OUTLINE PT0048A LQFP - 1.6 mm max height SCALE 2.000 LOW PROFILE QUAD FLATPACK 0.27 0.17 0.08 C A B 44X 0.5 4X 5.5 SEE DETAIL 1.6 MAX SEATING PLANE 0.1 C 1.45 0.25 1.35 GAGE PLANE 0.75 0.5 MIN 0 -7 0.45 DETAIL A...
  • Page 84 EXAMPLE BOARD LAYOUT PT0048A LQFP - 1.6 mm max height LOW PROFILE QUAD FLATPACK SYMM SEE SOLDER MASK DETAILS 48X (1.6) 48X (0.3) 44X (0.5) PKG SYMM (8.2) (R0.05) TYP (8.2) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE 10.000 0.05 MAX 0.05 MIN ALLAROUND ALL AROUND...
  • Page 85 EXAMPLE STENCIL DESIGN PT0048A LQFP - 1.6 mm max height LOW PROFILE QUAD FLATPACK SYMM 48X (1.6) 48X (0.3) 44X (0.5) PKG SYMM (8.2) (R0.05) TYP (8.2) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 10X 4215159/A 12/2021 NOTES: (continued) 7.
  • Page 86 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H...
  • Page 87 GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 5 x 5, 0.5 mm pitch Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com...
  • Page 88 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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