Motorola DSP56156 Manual page 64

t0 t1 t2 t3 t0 t1 t2 tw t2 t3 t0 t1 t2 t3 t0 t1 t2 tw t2 tw t2 t3
CLKO
TA
BS
t0 t1 t2 tw t2 tw t2 tw t2 t3 t0 t1 t2 tw t2 tw t2 t3 t0 t1 t2
CLKO
TA
BS
BR (Bus Request) - active low output when in master mode, active low input
when in slave mode. After power-on reset, this pin is an input (slave mode).
In this mode, the bus request BR allows another device such as a processor or
DMA controller to become the master of the DSP external data bus D0-D15 and
external address bus A0-A15. The DSP asserts BG a few T states after the BR
input is asserted. The DSP bus controller will release control of the external
data bus D0-D15, address bus A0-A15 and bus control pins PS/ DS, RD, WR,
and R/W at the earliest time possible consistent with proper synchronization.
These pins will then be placed in the high impedance state and the BB pin will
be deasserted. The DSP will continue executing instructions only if internal pro-
gram and data memory resources are being accessed. If the DSP requests the
external bus while BR input pin is asserted, the DSP bus controller inserts wait
states until the external bus becomes available (BR and BB deasserted). Note
that interrupts are not serviced when a DSP instruction is waiting for the bus
controller. Note also that BR is prevented from interrupting the execution of a
read/ modify/ write instruction.
If the master bit in the OMR register is set, this pin becomes an output (Master
Mode). In this mode, the DSP is not the external bus master and has to assert
BR to request the bus mastership. The DSP bus controller will insert wait states
until BG input is asserted and will then begin normal bus accesses after the ris-
MOTOROLA
BUS CONTROL (9 PINS)
Figure 2-3 TA Controlled Accesses
DSP56156 PIN DESCRIPTIONS 2 - 7