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INTERFACE WITH THE DSP56156 CORE PROCESSOR
6.4.2
On-chip Codec Programming Model
Figure 6-3 shows the four memory mapped registers (mapped into three memory loca-
tions) used by the on-chip codec.
On-chip Codec DATA REGISTERS
15
15
On-chip Codec CONTROL and STATUS REGISTERS
15
14
13
COIE
COE
INS
7
6
*
*
7
6
*
*
* - reserved bits, read as zero, should be written with zero for future compatibility
Figure 6-3 On-Chip Codec Programming Model
6.4.3
Codec Receive Register (CRX)
The CRX Codec Receive Register is used for A/D to DSP core data transfers. The CRX
register is viewed as a 16-bit read-only register by the DSP core. The CRX register is load-
ed with 16-bit data from the A/D section comb filter output. This transfer operation sets the
CRDF bit in the codec status register COSR. Reading CRX clears CRDF. The DSP may
program the COIE bit to cause a Codec Interrupt when CRDF is set.
6.4.4
Codec Transmit Register (CTX)
The CTX Codec Transmit Register is used for DSP core to D/A data transfers. The CTX
register is viewed as a 16-bit write-only register by the DSP core. Writing the CTX register
6 - 6
8
7
CRX REGISTER
8
7
CTX REGISTER
12
11
10
MGS1 MGS0
MUT
5
4
3
2
*
*
VC3
VC2
5
4
3
2
*
*
CRDF CTDE CROE CTUE
DSP56156 ON-CHIP SIGMA/DELTA CODEC
0
READ-ONLY CODEC
WRITE-ONLY CODEC
0
9
8
CRS1 CRS0
CODEC CONTROL
REGISTER (COCR)
1
0
ADDRESS $FFC8
VC1
VC0
1
0
REGISTER (COSR)
ADDRESS $FFE8
RECEIVE DATA
REGISTER
(Addr X:$FFE9)
TRANSMIT DATA
REGISTER
(Addr X:$FFE9)
READ-WRITE
READ-ONLY
CODEC STATUS
MOTOROLA
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