Motorola DSP56156 Manual page 37

Address MUX
Host
Interface
SSI0
SSI1
Timer
PLL
1 - 16
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
External
External
Data Switch
Bus
Control
Port
B I/O
Port
C I/O
Codec
DSP56156 OVERVIEW
Default
Function
A0-A15
D0-D15
BS
TA
PS/DS
TS
R/W
BR
BG
BB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
Mic
Aux
SPKP
SPKM
Bias
Vref
Vdiv
Alternate
Function
H0-H7
HA0
HA1
HA2
HR/W
HEN
HREQ
HACK
STD0
SRD0
SCK0
SC10
SC00
STD1
SRD1
SCK1
SC11
SC01
Tin
Tout
MOTOROLA