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15 Quad Synchronous Serial Interface (QSPI)
15.2.3 Pin Functions in Master Mode and Slave Mode
The pin functions are changed according to the transfer direction, transfer mode, and master/slave mode selections.
The differences in pin functions between the modes are shown in Table 15.2.3.1.
Pin
Single transfer mode Dual transfer mode Quad transfer mode Single transfer mode Dual transfer mode Quad transfer mode
QSDIOn[3:2] Always placed into Hi-Z state.
QSDIOn1
Always placed into
input state.
QSDIOn0
Always placed into
output state.
QSPICLKn
Outputs the QSPI clock to external devices.
Output clock polarity and phase can be configured if nec-
essary.
#QSPISSn
This pin is used to output the slave select signal in mas-
ter mode. In memory mapped access mode, this pin is
controlled by the internal state machine. In register ac-
cess mode, this pin is controlled by a register bit. When
connecting more than one external slave device, general-
purpose I/O ports can be used to output the extra slave
select signals.
15.2.4 Input Pin Pull-Up/Pull-Down Function
The QSPI pins (QSDIOn[3:0] pins in master mode or QSDIOn[3:0] pins, QSPICLKn, and #QSPISSn pins in slave
mode) have a pull-up or pull-down function as shown in Table 15.2.4.1. This function is enabled by setting the
QSPI_nMOD.PUEN bit to 1.
Pin
QSDIOn[3:0]
QSPICLKn
#QSPISSn
15.3 Clock Settings
15.3.1 QSPI Operating Clock
Operating clock in master mode
In master mode, the QSPI operating clock is supplied from the 16-bit timer. The following two options are pro-
vided for the clock configuration.
Use the 16-bit timer operating clock without dividing
By setting the QSPI_nMOD.NOCLKDIV bit to 1, the operating clock CLK_T16_m, which is configured
by selecting a clock source and a division ratio, for the 16-bit timer channel corresponding to the QSPI
channel is input to the QSPI as CLK_QSPIn. Since this clock is also used as the QSPI clock QSPICLKn
without changing, the CLK_QSPIn frequency becomes the baud rate.
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator.
It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit
timer channel are set (1 or 0).
15-6
Table 15.2.3.1 Pin Function Differences between Modes
Function in master mode
T h e s e p i n s a r e
T h e s e p i n s a r e
placed into input
o r o u t p u t s t a t e
placed into input
according to the
o r o u t p u t s t a t e
according to the
QSPI_nCTL.DIR bit
QSPI_nCTL.DIR bit
setting.
setting.
Table 15.2.4.1 Pull-Up or Pull-Down of QSPI Pins
Master mode
Pull-up
–
–
Seiko Epson Corporation
Function in slave mode
Always placed into Hi-Z state.
Always placed into
T h e s e p i n s a r e
input state.
placed into output
state while a low
This pin is placed
l e v e l i s a p p l i e d
into output state
to the #QSPISSn
while a low level
pin and the QSPI_
is applied to the
nCTL.DIR bit is set
#QSPISSn pin or
to 0 (output), or
placed into Hi-Z
placed into Hi-Z
state while a high
state while a high
level is applied to
level is applied to
the #QSPISSn pin.
the #QSPISSn pin
or the QSPI_nCTL.
DIR bit is set to 1
(input).
Inputs an external QSPI clock.
Clock polarity and phase can be designated according to
the input clock.
Applying a low level to the #QSPISSn pin enables the
QSPI to transmit/receive data. While a high level is applied
to this pin, the QSPI is not selected as a slave device. Data
input to the QSDIOn pins and the clock input to the QSPI-
CLKn pin are ignored. When a high level is applied, the
transmit/receive bit count is cleared to 0 and the already
received bits are discarded.
Slave mode
Pull-up
QSPI_nMOD.CPOL bit = 1: Pull-up
QSPI_nMOD.CPOL bit = 0: Pull-down
Pull-up
S1C31D41 TECHNICAL MANUAL
T h e s e p i n s a r e
placed into output
state while a low
l e v e l i s a p p l i e d
to the #QSPISSn
pin and the QSPI_
nCTL.DIR bit is set
to 0 (output), or
placed into Hi-Z
state while a high
level is applied to
the #QSPISSn pin
or the QSPI_nCTL.
DIR bit is set to 1
(input).
(Rev. 1.1)
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