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12.2.3 Pin Functions in Master Mode and Slave Mode
The pin functions are changed according to the master or slave mode selection. The differences in pin functions be-
tween the modes are shown in Table 12.2.3.1.
Pin
Function in master mode
SDIn
SDOn
Always placed into output state.
SPICLKn Outputs the SPI clock to external devices.
Output clock polarity and phase can be configured
if necessary.
#SPISSn Not used.
This input function is not required to be assigned to
the port. To output the slave select signal in master
mode, use a general-purpose I/O port function.
12.2.4 Input Pin Pull-Up/Pull-Down Function
The SPIA input pins (SDIn in master mode or SDIn, SPICLKn, and #SPISSn pins in slave mode) have a pull-up or
pull-down function as shown in Table 12.2.4.1. This function is enabled by setting the SPInMOD.PUEN bit to 1.
Pin
SDIn
SPICLKn
#SPISSn
12.3 Clock Settings
12.3.1 SPIA Operating Clock
Operating clock in master mode
In master mode, the SPIA operating clock is supplied from the 16-bit timer. The following two options are pro-
vided for the clock configuration.
Use the 16-bit timer operating clock without dividing
By setting the SPInMOD.NOCLKDIV bit to 1, the operating clock CLK_T16_m, which is configured by
selecting a clock source and a division ratio, for the 16-bit timer channel corresponding to the SPIA channel
is input to SPIA as CLK_SPIAn. Since this clock is also used as the SPI clock SPICLKn without changing,
the CLK_SPIAn frequency becomes the baud rate.
To supply CLK_SPIAn to SPIA, the 16-bit timer clock source must be enabled in the clock generator. It
does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit
timer channel are set (1 or 0).
When setting this mode, the timer function of the corresponding 16-bit timer channel may be used for an-
other purpose.
Use the 16-bit timer as a baud rate generator
By setting the SPInMOD.NOCLKDIV bit to 0, SPIA inputs the underflow signal generated by the corre-
sponding 16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro-
priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated
by the equations shown below.
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Table 12.2.3.1 Pin Function Differences between Modes
Always placed into input state.
Table 12.2.4.1 Pull-Up or Pull-Down of Input Pins
Master mode
Pull-up
–
–
Seiko Epson Corporation
12 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Function in slave mode
This pin is placed into output state while a low level
is applied to the #SPISSn pin or placed into Hi-Z
state while a high level is applied to the #SPISSn
pin.
Inputs an external SPI clock.
Clock polarity and phase can be designated accord-
ing to the input clock.
Applying a low level to the #SPISSn pin enables
SPIA to transmit/receive data. While a high level is
applied to this pin, SPIA is not selected as a slave
device. Data input to the SDIn pin and the clock
input to the SPICLKn pin are ignored. When a high
level is applied, the transmit/receive bit count is
cleared to 0 and the already received bits are dis-
carded.
Slave mode
Pull-up
SPInMOD.CPOL bit = 1: Pull-up
SPInMOD.CPOL bit = 0: Pull-down
Pull-up
12-3
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