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6.2.4 CMOS Output and High Impedance State
The I/O cells except for analog output can output signals in the V
put into high-impedance (Hi-Z) state.
6.2.5 High-/Low-level High-Current Drive Outputs
The ports with this type of output cell can directly drive an LED. For the drive capability, refer to "Input/Output
Port (PPORT) Characteristics" in the "Electrical Characteristics" chapter.
6.3 Clock Settings
6.3.1 PPORT Operating Clock
When using the chattering filter for entering external signals to PPORT, the PPORT operating clock CLK_PPORT
must be supplied to PPORT from the clock generator.
The CLK_PPORT supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
2. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
3. Set the following PCLK register bits:
- PCLK.CLKSRC[1:0] bits
- PCLK.CLKDIV[3:0] bits
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Settings in Step 3 determine the input sampling time of the chattering filter.
6.3.2 Clock Supply in SLEEP Mode
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be
configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock
source.
If the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source is 1, the CLK_PPORT clock source is deacti-
vated during SLEEP mode and it disables the chattering filter function regardless of the PxCHATEN.PxCHATENy
bit setting (chattering filter enabled/disabled).
6.3.3 Clock Supply in DEBUG Mode
The CLK_PPORT supply during DEBUG mode should be controlled using the PCLK.DBRUN bit.
The CLK_PPORT supply to PPORT is suspended when the CPU enters DEBUG mode if the PCLK.DBRUN bit
= 0. After the CPU returns to normal mode, the CLK_PPORT supply resumes. The PPORT chattering filter stops
operating when the CLK_PPORT supply is suspended. If the chattering filter is enabled in PPORT, the input port
function is also deactivated. However, the control registers can be altered. If the PCLK.DBRUN bit = 1, the CLK_
PPORT supply is not suspended and the chattering filter will keep operating in DEBUG mode.
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
DD
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Seiko Epson Corporation
6 I/O PORTS (PPORT)
and V
levels. Also the GPIO ports may be
SS
6-3
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