The I2Cs Module Is Placed Into Transfer Standby State - Epson S1C17624 Technical Manual

2
21 i C SlaVe (i2CS)
note: If the I2CS module has sent back a NAK as the response to the address sent by the master when
the conditions shown below are all met, the master must wait for 33 µs or more before it can send
another slave address (except when the master sends the I2CS slave address again).
1. The transfer rate is set to 320 kbps or higher.
2. The asynchronous address detection function is enabled.
3. The I2CS module is placed into transfer standby state and OSC1 is used as the operating
clock (PCLK).
Data reception
The following describes a data receive procedure.
The I2CS module starts data receiving process when SELECTED is set to 1 and R/W is set to 0. The received
data bits are input from the SDA1 pin in sync with the SCL1 input clock sent from the master. When the eight-
bit data (MSB first) is received in the shift register, the received data is loaded to RDATA[7:0]/I2CS_RECV
register.
When the received data is loaded to RDATA[7:0], RXRDY/I2CS_ASTAT register is set to 1 to issue a request
to the application program to read RDATA[7:0]. An interrupt can be generated when RXRDY is set to 1, so the
received data should be read in the interrupt handler routine. RXRDY is cleared by reading the received data.
When the clock stretch function is disabled (default)
When the clock stretch function has been disabled, data must be read from the I2CS_RECV register within
2
7 cycles of the I C clock (SCL1 input clock) from RXRDY being set to 1.
When the clock stretch function is enabled
When the clock stretch function has been enabled, the I2CS module pulls down the SCL1 pin to low to gen-
erate a clock stretch (wait) status until the received data is read from the I2CS_RECV register.
If the next data has been received without reading the received data, RDATA[7:0] will be overwritten. In this
case, RXOVF/I2CS_STAT register is set to 1 to indicate that the received data has been overwritten. An inter-
rupt can be generated when RXOVF is set to 1, so an error handling should be performed in the interrupt han-
dler routine. RXOVF is cleared by writing 1.
To return naK during data reception
During data reception (master transmission), the I2CS module sends back an ACK (SDA1 = low) every time an
8-bit data has been received (by default setting). The response code can be changed to NAK (SDA1 = Hi-Z) by
setting NAK_ANS/I2CS_CTL register. An ACK will be sent when NAK_ANS is 0 or a NAK will be sent when
NAK_ANS is set to 1.
NAK_ANS should be set within 7 cycles of the I
by receiving data just prior to one required for returning NAK.
SCL1 (input)
SDA1 (input)
SDA1 (output)
RXRDY
NAK_ANS
end of data transfer (detecting stop condition)
Data transfers will be terminated when the master generates a stop condition. The stop condition is a state in
which the SDA line is pulled up from Low to High with the SCL line maintained at High.
21-6
6 7 8 9 1
D2 D1 D0 D7
ACK
Receive interrupt
Figure 21. 5.3 NAK_ANS Setting and NAK Response Timing
Seiko epson Corporation
2 C clock (SCL1 input clock) after RXRDY has been set to 1
2 3 4 5
D6 D5 D4 D3 D2
NAK_ANS setting period
S1C17624/604/622/602/621 TeChniCal Manual
6 7 8 9
D1 D0
NAK